JAJSK12C September   2020  – December 2021 TPS542A50

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Enable and Adjustable Undervoltage Lockout
      2. 7.3.2  Input and VREG Undervoltage Lockout Protection
      3. 7.3.3  Voltage Reference and Setting the Output Voltage
      4. 7.3.4  Remote Sense Function
      5. 7.3.5  Switching Frequency
      6. 7.3.6  Voltage Control Mode Internal Compensation
      7. 7.3.7  Soft Start and Prebiased Output Start-up
      8. 7.3.8  Power Good
      9. 7.3.9  Overvoltage and Undervoltage Protection
      10. 7.3.10 Overcurrent Protection
      11. 7.3.11 High-Side FET Throttling
      12. 7.3.12 Overtemperature Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Pulse-Frequency Modulation Eco-mode Light Load Operation
      2. 7.4.2 Forced Continuous-Conduction Mode
      3. 7.4.3 Soft Start
    5. 7.5 Programming
      1. 7.5.1 I2C Address Selection
      2. 7.5.2 Powering Device Into Programming Mode
      3. 7.5.3 Device Configuration
      4. 7.5.4 Output Voltage Adjustment
    6. 7.6 Pin-Strap Programming
    7. 7.7 Register Maps
      1. 7.7.1 ID Register (Offset = 0x0) [reset = 0x21]
      2. 7.7.2 STATUS Register (Offset = 0x1) [reset = 0x0]
      3. 7.7.3 VOUT_ADJ1 Register (Offset = 0x2) [reset = 0x0]
      4. 7.7.4 VOUT_ADJ2 Register (Offset = 0x3) [reset = 0x0]
      5. 7.7.5 CONFIG1 Register (Offset = 0x4) [reset = 0x0B]
      6. 7.7.6 CONFIG2 Register (Offset = 0x5) [reset = 0x2D]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Full Analog Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Custom Design With WEBENCH® Tools
          2. 8.2.1.2.2  Output Voltage Calculation
          3. 8.2.1.2.3  Switching Frequency Selection
          4. 8.2.1.2.4  Inductor Selection
          5. 8.2.1.2.5  Input Capacitor Selection
          6. 8.2.1.2.6  Bootstrap Capacitor Selection
          7. 8.2.1.2.7  R-C Snubber and VIN Pin High-Frequency Bypass
          8. 8.2.1.2.8  Output Capacitor Selection
          9. 8.2.1.2.9  Response to a Load Transient
          10. 8.2.1.2.10 Pin-Strap Setting
        3. 8.2.1.3 Application Curves
        4. 8.2.1.4 Typical Application Circuits
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Fusion Digital Power™ Designer Tool
        2. 11.1.1.2 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.6 Voltage Control Mode Internal Compensation

The TPS542A50 has 15 unique internal compensation settings to cover a wide range of output inductors and capacitors. For each switching frequency option, there are four compensation options that can be chosen using a single resistor to ground on the COMP pin or through I2C programming.

In addition to selecting the compensation option, the COMP pin also selects the device I2C address. The following compensation settings and I2C address combinations can be programmed on the COMP pin.

Table 7-2 Compensation and I2C Address Resistor Selection
RCOMP (kΩ)I2C ADDRESSCOMPENSATION SETTING
Short0x60COMP 2
7.50x60COMP 1
18.2COMP 2
26.1COMP 3
35.7COMP 4
47.50x61COMP 1
61.9COMP 2
78.7COMP 3
102COMP 4

Each compensation network consists of two zeros and one high frequency pole. Table 7-3 maps the compensation settings to the first zero frequency at different output voltage range, second zero frequency, and high frequency pole.

Table 7-3 Compensation Settings
FREQUENCY (kHz) COMPENSATION SETTING ZERO 1 (kHz) FOR VOUT = 0.5 V-1.1 V ZERO 1 (kHz) for VOUT = 1.2 V-1.5 V ZERO 1 (kHz) FOR VOUT = 1.6 V-2.8 V ZERO 1 (kHz) FOR VOUT = 2.9 V-4.0 V ZERO 1 (kHz) for VOUT = 4.1 V-5.5 V ZERO 2 (kHz) POLE (kHz)
400 COMP 1 2.2 2.1 1.8 1.6 1.2 5.5 60
COMP 2 2.2 2.1 1.8 1.6 1.2 7.3 80
COMP 3 3.6 3.4 3.0 2.7 2.0 14.5 159
COMP 4 7.2 7.0 6.1 5.4 4.1 28.4 312
600 COMP 1 2.2 2.1 1.8 1.6 1.2 5.5 60
COMP 2 2.7 2.6 2.3 2.0 1.5 11.0 121
COMP 3 4.5 4.3 3.8 3.4 2.5 18.1 199
COMP 4 10.5 10.1 8.8 7.9 5.9 45.2 497
800 COMP 1 2.2 2.1 1.8 1.6 1.2 7.3 80
COMP 2 3.6 3.4 3.0 2.7 2.0 14.5 159
COMP 3 7.2 7.0 6.0 5.4 4.1 28.4 312
COMP 4 13.5 13 11.4 10.1 7.6 55.6 612
1000 COMP 1 2.2 2.1 1.9 1.7 1.2 9.0 99
COMP 2 4.5 4.3 3.8 3.4 2.5 18.1 199
COMP 3 9.0 8.7 7.6 6.7 5.1 37.1 408
COMP 4 18.8 18.2 15.9 14.1 10.6 72.3 796
1200 COMP 1 2.7 2.6 2.3 2.0 1.5 11.0 121
COMP 2 4.5 4.3 3.8 3.4 2.5 18.1 199
COMP 3 10.5 10.1 8.8 7.9 5.9 45.2 497
COMP 4 23.5 22.7 19.9 17.7 13.3 90.4 995
2000 COMP 1 4.5 4.3 3.8 3.4 2.5 18.1 199
COMP 2 9 8.7 7.6 6.7 5.1 37.1 408
COMP 3 18.8 18.2 15.9 14.1 10.6 72.3 796
COMP 4 37.7 36.4 31.8 28.3 21.2 144.7 1592
2200 COMP 1 4.5 4.3 3.8 3.4 2.5 18.1 199
COMP 2 9 8.7 7.6 6.7 5.1 37.1 408
COMP 3 18.8 18.2 15.9 14.1 10.6 72.3 796
COMP 4 37.7 36.4 31.8 28.3 21.2 144.7 1592

Table 7-4 shows the second zero frequency placement about two times based on a ratio (fO/fSW) of the LC frequency (fO) to the switching frequency and lists the values in Table 7-3. The second zero frequency does not change with the output voltage. The high frequency pole is about 10 times of the second zero frequency to attenuate the switching frequency noise and to have a safe gain margin.

The output filter LC frequency must be designed between the first and second zero frequencies. The ratio of the LC frequency to the switching frequency in Table 7-4 is a guide to select the LC frequency fO. For example, the LC frequency for 1-MHz switching frequency is 10 kHz at 1% ratio. Given 1-V output voltage, COMP2 has the first zero at 4.5 kHz to compensate the LC filter double poles. For the same LC filter and switching frequencies of 3.3-V output voltage, COMP3 has the first zero at 6.7 kHz to compensate the LC filter double poles. The compensation setting needs to consider for the output capacitor derating, especially ceramic capacitor, and inductor tolerance. It is recommended to verify the load transient and bode plot based upon the compensation selection.

Table 7-4 Second Zero Frequency
fO/fSW COMPENSATION SETTING SECOND ZERO FREQUENCY
0.5% COMP 1 ~2X of 0.5% fO/fSW
1% COMP 2 ~2X of 1% fO/fSW
2% COMP 3 ~2X of 2% fO/fSW
4% COMP 4 ~2X of 4% fO/fSW