JAJSDJ4D March   2016  – July 2017 TPS548D22

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5  Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 40-A FET
      2. 8.3.2 On-Resistance
      3. 8.3.3 Package Size, Efficiency and Thermal Performance
      4. 8.3.4 Soft-Start Operation
      5. 8.3.5 VDD Supply Undervoltage Lockout (UVLO) Protection
      6. 8.3.6 EN_UVLO Pin Functionality
      7. 8.3.7 Fault Protections
        1. 8.3.7.1 Current Limit (ILIM) Functionality
        2. 8.3.7.2 VDD Undervoltage Lockout (UVLO)
        3. 8.3.7.3 Overvoltage Protection (OVP) and Undervoltage Protection (UVP)
        4. 8.3.7.4 Out-of-Bounds Operation
        5. 8.3.7.5 Overtemperature Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 DCAP3 Control Topology
      2. 8.4.2 DCAP Control Topology
    5. 8.5 Programming
      1. 8.5.1 Programmable Pin-Strap Settings
        1. 8.5.1.1 Frequency Selection (FSEL) Pin
        2. 8.5.1.2 VSEL Pin
        3. 8.5.1.3 DCAP3 Control and Mode Selection
          1. 8.5.1.3.1 Application Workaround to Support 4-ms and 8-ms SS Settings
      2. 8.5.2 Programmable Analog Configurations
        1. 8.5.2.1 RSP/RSN Remote Sensing Functionality
          1. 8.5.2.1.1 Output Differential Remote Sensing Amplifier
        2. 8.5.2.2 Power Good (PGOOD Pin) Functionality
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 TPS548D22 1.5-V to 16-V Input, 1-V Output, 40-A Converter
      2. 9.2.2 Design Requirements
      3. 9.2.3 Design Procedure
        1. 9.2.3.1  Switching Frequency Selection
        2. 9.2.3.2  Inductor Selection
        3. 9.2.3.3  Output Capacitor Selection
          1. 9.2.3.3.1 Minimum Output Capacitance to Ensure Stability
          2. 9.2.3.3.2 Response to a Load Transient
          3. 9.2.3.3.3 Output Voltage Ripple
        4. 9.2.3.4  Input Capacitor Selection
        5. 9.2.3.5  Bootstrap Capacitor Selection
        6. 9.2.3.6  BP Pin
        7. 9.2.3.7  R-C Snubber and VIN Pin High-Frequency Bypass
        8. 9.2.3.8  Optimize Reference Voltage (VSEL)
        9. 9.2.3.9  MODE Pin Selection
        10. 9.2.3.10 Overcurrent Limit Design.
      4. 9.2.4 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
      1. 11.2.1 Mounting and Thermal Profile Recommendation
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報
  14. 14Package Option Addendum
    1. 14.1 Packaging Information
    2. 14.2 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Description (continued)

TPS548D22デバイスは、7mm×5mmの40ピンLQFN-CLIP (RVF)パッケージで供給されます(RoHS指令対象外)。