8.3.7.1 Current Limit (ILIM) Functionality

Figure 15. Current Limit Resistance vs OCP Valley Overcurrent Limit

The ILIM pin sets the OCP level. Connect the ILIM pin to GND through the voltage setting resistor, R_ILIM. In order to provide both good accuracy and cost effective solution, TPS548D22 device supports temperature compensated internal MOSFET R_DS(on) sensing.

Also, the TPS548D22 device performs both positive and negative inductor current limiting with the same magnitudes. The positive current limit normally protects the inductor from saturation that causes damage to the high-side FET and low-side FET. The negative current limit protects the low-side FET during OVP discharge.

The voltage between GND pin and SW pin during the OFF time monitors the inductor current. The current limit has 3000 ppm/°C temperature slope to compensate the temperature dependency of the on-resistance (R_DS(on)). The GND pin is used as the positive current sensing node.

TPS548D22 device uses cycle-by-cycle over-current limiting control. The inductor current is monitored during the OFF state and the controller maintains the OFF state during the period that the inductor current is larger than the overcurrent ILIM level. V_ILIM sets the valley level of the inductor current.

8.3.7.2 VDD Undervoltage Lockout (UVLO)

The TPS548D22 device has an UVLO protection function for the VDD supply input. The on-threshold voltage is 4.25 V with 200 mV of hysteresis. During a UVLO condition, the device is disabled regardless of the EN_UVLO pin voltage. The supply voltage (V_VDD) must be above the on-threshold to begin the pin strap detection.

8.3.7.3 Overvoltage Protection (OVP) and Undervoltage Protection (UVP)

The device monitors a feedback voltage to detect overvoltage and undervoltage. When the feedback voltage becomes lower than 68% of the target voltage, the UVP comparator output goes high and an internal UVP delay counter begins counting. After 1 ms, the device latches OFF both high-side and low-side MOSFETs drivers. The UVP function enables after soft-start is complete.

When the feedback voltage becomes higher than 120% of the target voltage, the OVP comparator output goes high and the circuit latches OFF the high-side MOSFET driver and turns on the low-side MOSFET until reaching a negative current limit. Upon reaching the negative current limit, the low-side FET is turned off and the high-side FET is turned on again for a minimum on-time. The TPS548D22 device operates in this cycle until the output voltage is pulled down under the UVP threshold voltage for 1 ms. After the 1-ms UVP delay time, the high-side FET is latched off and low-side FET is latched on. The fault is cleared with a reset of VDD or by retoggling the EN pin.

8.3.7.4 Out-of-Bounds Operation

The device has an out-of-bounds (OOB) overvoltage protection that protects the output load at a much lower overvoltage threshold of 8% above the target voltage. OOB protection does not trigger an overvoltage fault, so the device is not latched off after an OOB event. OOB protection operates as an early no-fault overvoltage-protection mechanism. During the OOB operation, the controller operates in forced PWM mode only by turning on the low-side FET. Turning on the low-side FET beyond the zero inductor current quickly discharges the output capacitor thus causing the output voltage to fall quickly toward the setpoint. During the operation, the cycle-by-cycle negative current limit is also activated to ensure the safe operation of the internal FETs.

8.3.7.5 Overtemperature Protection

TPS548D22 device has overtemperature protection (OTP) by monitoring the die temperature. If the temperature exceeds the threshold value (default value 165°C), TPS548D22 device is shut off. When the temperature falls about 25°C below the threshold value, the device turns on again. The OTP is a non-latch protection.

8.5.1.1 Frequency Selection (FSEL) Pin

The TPS548D22 device allows users to select the switching frequency, light load and internal ramp amplitude by using FSEL pin. Table 2 lists the divider resistor values for the selection. The 1% tolerance resistors with typical temperature coefficient of ±100ppm/°C are recommended. Higher performance resistors can be used if tighter noise margin is required for more reliable frequency selection detection.

FSEL pin strap configuration programs the switching frequency, internal ramp compensation and light load conduction mode.

8.5.1.2 VSEL Pin

VSEL pin strap configuration is used to program initial boot voltage value, hiccup mode, and latch-off mode. The initial boot voltage is used to program the main loop voltage reference point. VSEL voltage settings provide TI designated discrete internal reference voltages. Table 3 lists internal reference voltage selections.

8.5.1.3 DCAP3 Control and Mode Selection

The MODE pinstrap configuration programs the control topology and internal soft-start timing selections. The TPS548D22 device supports both DCAP3 and DCAP operation

MODE[4] selection bit is used to set the control topology. If MODE[4] bit is 0, it selects DCAP operation. If MODE[4] bit is 1, it selects DCAP3 operation.

MODE[1] and MODE[0] selection bits are used to set the internal soft-start timing.

8.5.1.3.1 Application Workaround to Support 4-ms and 8-ms SS Settings

In order to properly design for 4-ms and 8-ms SS settings, additional application consideration is needed. The recommended application workaround to support the 4-ms and 8-ms soft-start settings is to ensure sufficient time delay between the VDD and EN_UVLO signals. The minimum delay between the rising maximum VDD_UVLO level and the minimum turnon threshold of EN_UVLO is at least T_{DELAY_MIN}.

Equation 1. T_{DELAY_MIN} = K × V_REF

where

• K = 9 ms/V for SS setting of 4 ms
• K = 18 ms/V for SS setting of 8 ms
• V_REF is the internal reference voltage programmed by VSEL pin strap

For example, if SS setting is 4 ms and V_REF = 1 V, program the minimum delay at least 9 ms; if SS setting is 8 ms, the minimum delay should be programmed at least 18 ms. See Figure 16 and Figure 17 for detailed timing requirement.

Figure 16. Proper Sequencing of V_DD and EN_UVLO to Support the use of 4-ms SS Setting

Figure 17. Minimum Delay Between V_DD and EN_UVLO to Support the use of 4-ms and 8-ms SS settings

The workaround/consideration described previously is not required for SS settings of 1 ms and 2 ms.

8.5.2.1 RSP/RSN Remote Sensing Functionality

RSP and RSN pins are used for remote sensing purpose. In the case where feedback resistors are required for output voltage programming, the RSP pin must be connected to the mid-point of the resistor divider, and the RSN pin must always be connected to the load return. In the case where feedback resistors are not required, such as when the VSEL programs the output voltage setpoint, the RSP pin must be connected to the positive sensing point of the load, and the RSN pin should always be connected to the load return.

RSP and RSN pins are extremely high-impedance input terminals of the true differential remote sense amplifier. The feedback resistor divider should use resistor values much less than 100 kΩ.

8.5.2.1.1 Output Differential Remote Sensing Amplifier

The examples in this section show simplified remote sensing circuitry where each example uses an internal reference of 1 V. Figure 18 shows remote sensing without feedback resistors, with an output voltage set point of 1 V. Figure 19 shows remote sensing using feedback resistors, with an output voltage set point of 5 V.

Figure 18. Remote Sensing Without Feedback Resistors

Figure 19. Remote Sensing With Feedback Resistors

8.5.2.2 Power Good (PGOOD Pin) Functionality

The TPS548D22 device has power-good output that registers high when switcher output is within the target. The power-good function is activated after soft-start has finished. When the soft-start ramp reaches 300 mV above the internal reference voltage, SSend signal goes high to enable the PGOOD detection function. If the output voltage becomes within ±8% of the target value, internal comparators detect power-good state and the power good signal becomes high after an 8-ms programmable delay. If the output voltage goes outside of ±16% of the target value, the power good signal becomes low after two microsecond (2-µs) internal delay. The open-drain power-good output must be pulled up externally. The internal N-channel MOSFET does not pull down until the VDD supply is above 1.2 V.