JAJSPC6 November 2023 TPS61377
PRODUCTION DATA
- 1
- 1 特長
- 2 アプリケーション
- 3 概要
- 4 Device Comparison Table
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Device and Documentation Support
- 10Revision History
- 11Mechanical, Packaging, and Orderable Information
8.2.2.6 Loop Stability
The TPS61377 requires external compensation, which allows the loop response to be optimized for each application. The COMP pin is the output of the internal error amplifier. An external compensation network, comprised of resistor RC, and ceramic capacitors CC and CP, is connected to the COMP pin.
The power stage small signal loop response of constant off-time (COT) with peak current control can be modeled by Equation 11.
where
- D is the switching duty cycle.
- RO is the output load resistance.
- KCOMP is power stage trans-conductance (inductor peak current / comp voltage), which is 6.5 A/V.
where
- CO is effective output capacitance.
where
- RESR is the equivalent series resistance of the output capacitor.
The COMP pin is the output of the internal transconductance amplifier. Equation 15 shows the small signal transfer function of compensation network.
where
- GEA is the transconductance of the amplifier, which is 240 uS.
- REA is the output resistance of the amplifier, which is 100 MΩ.
- VREF is the reference voltage at the FB pin.
- VOUT is the output voltage.
- ƒCOMP1, ƒCOMP2 are the frequency of the poles of the compensation network.
- ƒCOMZ is the zero's frequency of the compensation network.
The next step is to choose the loop crossover frequency, ƒC. The higher frequency that the loop gain stays above zero before crossing over, the faster the loop response is. It is generally accepted that the loop gain cross over no higher than the lower of either 1/10 of the switching frequency, ƒSW, or 1/5 of the RHPZ frequency, ƒRHPZ.
Then set the value of RC, CC, and CP (in Figure 8-1) by following these equations.
where
- ƒC is the selected crossover frequency.
The value of CC can be set by Equation 17.
The value of CP can be set by Equation 18.
If the calculated value of CP is less than 10 pF, it can be left open.
Designing the loop for greater than 45° of phase margin and greater than 10-dB gain margin eliminates output voltage ringing during the line and load transient.