JAJSPC6 November 2023 TPS61377
PRODUCTION DATA
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NUMBER | ||
VIN | 1 | I | IC power supply input |
EN/UVLO | 2 | I | Enable logic input and programmable input voltage undervoltage lockout (UVLO) input. Logic
high level enables the device. Logic low level disables the device
and turns it into shutdown mode. The converter start-up and shutdown
levels can be programmed by connecting this pin to the supply
voltage through a resistor divider. This pin must not be left floating and must be terminated. |
MODE | 3 | I | Operating mode selection pin for the device in light load condition. When this pin is logic low, the device operates in auto PFM mode. When this pin is logic high, the device operates in forced PWM mode. |
VSENSE | 4 | I | Output voltage sense |
VOUT | 5 | PWR | Boost converter output |
SW | 6 | PWR | The switching node pin of the converter. It is connected to the drain of the internal low-side power MOSFET and the source of the internal high-side power MOSFET. |
PGND | 7 | PWR | Power ground of the IC |
FB | 8 | I | Output voltage feedback pin. Connect to the center tap of a resistor divider to program the output voltage. |
COMP | 9 | O | Output of the internal error amplifier. Connect the loop compensation network between this pin and the AGND pin. |
ILIM | 10 | I | Programmable switch peak current limit. An external resistor must be connected between this pin and the AGND pin. |
VCC | 11 | O | Output of the internal regulator. A ceramic capacitor of more than 1 μF is required between this pin and AGND. |
AGND | 12 | PWR | Analog ground of the IC |
BOOT | 13 | O | Power supply for high side MOSFET gate driver. A ceramic capacitor of 0.47 μF to 1 μF must be connected between this pin and the SW pin. |