JAJSJ58B january   2015  – august 2023 TPS62065-Q1 , TPS62067-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6.     Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Mode Selection (TPS62065-Q1) and Forced PWM Mode (TPS62067A-Q1)
      2. 9.3.2 Power Good (PG, TPS62067x-Q1)
      3. 9.3.3 Enable
      4. 9.3.4 Shutdown and Output Discharge
      5. 9.3.5 Soft Start
      6. 9.3.6 Undervoltage Lockout (UVLO)
      7. 9.3.7 Internal Current Limit and Foldback Current Limit For Short-Circuit Protection
      8. 9.3.8 Clock Dithering
      9. 9.3.9 Thermal Shutdown
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power Save Mode
        1. 9.4.1.1 Dynamic Voltage Positioning
        2. 9.4.1.2 100% Duty-Cycle Low-Dropout Operation
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Output Voltage Setting
        2. 10.2.2.2 Output Filter Design (Inductor And Output Capacitor)
          1. 10.2.2.2.1 Inductor Selection
          2. 10.2.2.2.2 Output Capacitor Selection
          3. 10.2.2.2.3 Input Capacitor Selection
        3. 10.2.2.3 Checking Loop Stability
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 サード・パーティ製品に関する免責事項
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.1 Overview

The TPS62065-Q1, TPS62067-Q1 step-down converters operates with 3-MHz (typical) fixed-frequency pulse-width modulation (PWM) at moderate to heavy load currents. At light load currents, the converter can automatically enter power save mode and then operate in pulse-frequency mode (PFM). The TPS62067A-Q1 operates with 3-MHz (typical) fixed-frequency pulse-width modulation (PWM) at all loads.

During PWM operation, the converter uses a unique fast-response voltage-mode controller scheme with input-voltage feedforward to achieve good line and load regulation, which allows the use of small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, the high-side MOSFET switch is turned on. The current flows from the input capacitor through the high-side MOSFET switch through the inductor to the output capacitor and load. During this phase, the current ramps up until the PWM comparator trips and the control logic turns off the switch. The current-limit comparator also turns off the switch in case the current-limit of the high-side MOSFET switch is exceeded. After a dead time preventing shoot-through current, the low-side MOSFET rectifier is turned on and the inductor current ramps down. The current now flows from the inductor to the output capacitor and to the load. The current returns back to the inductor through the low-side MOSFET rectifier.

The next cycle is initiated by the clock signal again turning off the low-side MOSFET rectifier and turning on the high-side MOSFET switch.