JAJSLL7B February   2023  – March 2024 TPS628301 , TPS628302 , TPS628303 , TPS628304

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Device Options
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information Discrete
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Pulse Width Modulation (PWM) Operation
      2. 7.3.2 Power Save Mode (PSM) Operation
      3. 7.3.3 Start-Up and Soft Start
      4. 7.3.4 Switch Cycle-by-Cycle Current Limit
      5. 7.3.5 Short-Circuit Protection
      6. 7.3.6 Undervoltage Lockout
      7. 7.3.7 Thermal Shutdown
      8. 7.3.8 Optimized EMI Performance
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable, Disable, and Output Discharge
      2. 7.4.2 Minimum Duty Cycle and 100% Mode Operation
      3. 7.4.3 Power Good
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Setting The Output Voltage
        3. 8.2.2.3 Inductor Selection
        4. 8.2.2.4 Output Capacitor Selection
        5. 8.2.2.5 Input Capacitor Selection
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Thermal Considerations
  10. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Short-Circuit Protection

In devices with hiccup protection, when a current limit event occurs for 32 consecutive switching cycles (about 16 µs), the device turns off the high-side FET for about 9.6 ms, during which time the inductor current decays through the low-side FET body diode. After 9.6 ms has expired, the device automatically starts switching again, beginning with a soft-start condition. The device alternates between bursts of switching cycles and 9.6-ms pauses for as long as the overload condition on the output exists.

In devices with latch-off protection, When a current limit event occurs for 32 consecutive switching cycles (about 16 µs), the device stops switching and latches off the high-side and low-side FETs. To recover normal operation after a latched short-circuit event, you must cycle VIN or EN.

In devices with latch-off protection, there is also an OVP protection circuit that uses the PG window comparator. An OVP event is detected when the FB voltage is approximately 110% × (0.5V) for a period longer than the deglitch time of 35 µs. In this case, the converter de-asserts the PG signal and performs the overvoltage protection function. The converter latches off both high-side and low-side FET and remains in this state. To recover normal operation after a latched short-circuit event, you must cycle VIN or EN.