JAJSK46A November   2020  – August 2021 TPS6521845

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     4
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Wake-Up and Power-Up and Power-Down Sequencing
        1. 7.3.1.1  Power-Up Sequencing
        2. 7.3.1.2  Power-Down Sequencing
        3. 7.3.1.3  Strobe 1 and Strobe 2
        4. 7.3.1.4  Supply Voltage Supervisor and Power-Good (PGOOD)
        5. 7.3.1.5  Backup Supply Power-Good (PGOOD_BU)
        6. 7.3.1.6  Internal LDO (INT_LDO)
        7. 7.3.1.7  Current Limited Load Switches
          1. 7.3.1.7.1 Load Switch 1 (LS1)
          2. 7.3.1.7.2 Load Switch 2 (LS2)
          3. 7.3.1.7.3 Load Switch 3 (LS3)
        8. 7.3.1.8  LDO1
        9. 7.3.1.9  Coin Cell Battery Voltage Acquisition
        10. 7.3.1.10 UVLO
        11. 7.3.1.11 Power-Fail Comparator
        12. 7.3.1.12 Battery-Backup Supply Power-Path
        13. 7.3.1.13 DCDC3 and DCDC4 Power-Up Default Selection
        14. 7.3.1.14 I/O Configuration
          1. 7.3.1.14.1 Configuring GPO2 as Open-Drain Output
          2. 7.3.1.14.2 Using GPIO3 as Reset Signal to DCDC1 and DCDC2
        15. 7.3.1.15 Push Button Input (PB)
          1. 7.3.1.15.1 Signaling PB-Low Event on the nWAKEUP Pin
          2. 7.3.1.15.2 Push Button Reset
        16. 7.3.1.16 AC_DET Input (AC_DET)
        17. 7.3.1.17 Interrupt Pin (INT)
        18. 7.3.1.18 I2C Bus Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
      2. 7.4.2 OFF
      3. 7.4.3 ACTIVE
      4. 7.4.4 SUSPEND
      5. 7.4.5 RESET
    5. 7.5 Register Maps
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Applications Without Battery Backup Supplies
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Filter Design
        2. 8.2.2.2 Inductor Selection for Buck Converters
        3. 8.2.2.3 Output Capacitor Selection
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Register Maps

7.5.1 Password Protection

Registers 0x11 through 0x26 are protected against accidental write by a 8-bit password. The password must be written prior to writing to a protected register and automatically resets to 0x00 after the next I2C transaction, regardless of the register accessed or transaction type (read or write). The password is required for write access only and is not required for read access.

To write to a protected register:

  1. Write the address of the destination register, XORed with the protection password (0x7D), to the PASSWORD register (0x10).
  2. Write the data to the password protected register.
  3. If the content of the PASSWORD register is XORed, with an address send that matches 0x7D, then the data transfers to the protected register. Otherwise, the transaction is ignored. In either case the PASSWORD register resets to 0x00 after the transaction.

The cycle must be repeated for any other register that is Level1 write protected.

7.5.2 Freshness Seal (FSEAL) Bit

The FSEAL (freshness seal) bit prevents accidental shut-down of the always-on supplies, DCDC5 and DCDC6. The FSEAL bit exists in a default state of 0b, and can be set to 1b and reset to 0b once for factory testing. The second time the bit is set to 1b, it remains 1b and cannot reset again under software control. Coin-cell battery and main supply must be disconnected from the device to reset the FSEAL bit again. With the FSEAL bit set to 1b, DCDC5 and DCDC6 are forced ON regardless of the state of the DC5_EN and DC6_EN bit, and the rails do not turn off when the device enters the OFF state.

A consecutive write of [0xB1, 0xFE, and 0xA3] to the password register sets the FSEAL bit to 1b. The three bytes must be written consecutively for the sequence to be valid. No other read or write transactions are allowed between the three bytes, or the sequence is invalid. After a valid sequence, the FSEAL bit in the STATUS register reflects the new setting.

After setting the FSEAL bit, the device can enter the OFF state or any other mode of operation without affecting the state of the FSEAL bit, provided the coin-cell supply remains connected to the chip.

A second write of [0xB1, 0xFE, and 0xA3] to the password register resets the FSEAL bit to 0b. The three bytes must be written consecutively for the sequence to be valid.

A third write of [0xB1, 0xFE, and 0xA3] to the password register sets the FSEAL bit to 1b and locks it into this state for as long as the coin-cell supply (CC) remains connected to the device.

7.5.3 FLAG Register

The FLAG register contains a bit for each power rail and GPO to keep track of the enable state of the rails while the system is suspended. The following rules apply to the FLAG register:

  • The power-up default value for any flag bit is 0.
  • Flag bits are read-only and cannot be written to.
  • Upon entering a SUSPEND state, the flag bits are set to same value as their corresponding ENABLE bits. Rails and GPOs enabled in a SUSPEND state have flag bits set to 1, while all other flag bits are set to 0. Flag bits are not updated while in the SUSPEND state or when exiting the SUSPEND state.
  • The FLAG register is static in WAIT_PWR_EN and ACTIVE state. The FLAG register reflects the enable state of DCDC1, DCDC2, DCDC3, DCDC4, and LDO1; and, reflects the enable state of GPO1, GPO2, and GPO3 during the last SUSPEND state.

The host processor reads the FLAG register to determine if the system powered up from the OFF or SUSPEND state. In the SUSPEND state, typically the DDR memory is kept in self refresh mode and therefore the DC3_FLG or DC4_FLG bits are set.

7.5.4 TPS6521845 Registers

Table 7-5 lists the memory-mapped registers for the TPS6521845. All register offset addresses not listed in Table 7-5 should be considered as reserved locations and the register contents should not be modified.

Table 7-5 TPS6521845 Registers
SUBADDRESS ACRONYM REGISTER NAME R/W PASSWORD PROTECTED SECTION
0x00 CHIPID CHIP ID R No Go
0x01 INT1 INTERRUPT 1 R No Go
0x02 INT2 INTERRUPT 2 R No Go
0x03 INT_MASK1 INTERRUPT MASK 1 R/W No Go
0x04 INT_MASK2 INTERRUPT MASK 2 R/W No Go
0x05 STATUS STATUS R No Go
0x06 CONTROL CONTROL R/W No Go
0x07 FLAG FLAG R No Go
0x10 PASSWORD PASSWORD R/W No Go
0x11 ENABLE1 ENABLE 1 R/W Yes Go
0x12 ENABLE2 ENABLE 2 R/W Yes Go
0x13 CONFIG1 CONFIGURATION 1 R/W Yes Go
0x14 CONFIG2 CONFIGURATION 2 R/W Yes Go
0x15 CONFIG3 CONFIGURATION 3 R/W Yes Go
0x16 DCDC1 DCDC1 CONTROL R/W Yes Go
0x17 DCDC2 DCDC2 CONTROL R/W Yes Go
0x18 DCDC3 DCDC3 CONTROL R/W Yes Go
0x19 DCDC4 DCDC4 CONTROL R/W Yes Go
0x1A SLEW SLEW RATE CONTROL R/W Yes Go
0x1B LDO1 LDO1 CONTROL R/W Yes Go
0x20 SEQ1 SEQUENCER 1 R/W Yes Go
0x21 SEQ2 SEQUENCER 2 R/W Yes Go
0x22 SEQ3 SEQUENCER 3 R/W Yes Go
0x23 SEQ4 SEQUENCER 4 R/W Yes Go
0x24 SEQ5 SEQUENCER 5 R/W Yes Go
0x25 SEQ6 SEQUENCER 6 R/W Yes Go
0x26 SEQ7 SEQUENCER 7 R/W Yes Go

Table 7-6 explains the common abbreviations used in this section.

Table 7-6 Common Abbreviations
Abbreviation Description
R Read
W Write
R/W Read and write capable
h Hexadecimal notation of a group of bits
b Hexadecimal notation of a bit or group of bits
X Do not care reset value

7.5.5 CHIPID Register (subaddress = 0x00) [reset = 0x45]

CHIPID is shown in Figure 7-36 and described in Table 7-7.

Return to Summary Table.

Figure 7-36 CHIPID Register
7 6 5 4 3 2 1 0
CHIP REV
R-8h R-5h
Table 7-7 CHIPID Register Field Descriptions
Bit Field Type Reset Description
7-3 CHIP R 8h

Chip ID:

0h = TPS65218

1h = Future use

2h = TPS6521815

3h = Future use

4h = TPS6521825

5h = Future use

6h = TPS6521835

7h = Future use

8h = TPS6521845

9h = Future use

Ah = TPS6521855

...

1Fh = Future use

2-0 REV R 5h

Revision code:

0h = Revision 1.0

1h = Revision 1.1

2h = Revision 2.0

3h = Revision 2.1

4h = Revision 3.0

5h = Revision 4.0 (D0)

6h = Future use

7h = Future use

7.5.6 INT1 Register (subaddress = 0x01) [reset = 0x00]

INT1 is shown in Figure 7-37 and described in Table 7-8.

Return to Summary Table.

Figure 7-37 INT1 Register
7 6 5 4 3 2 1 0
RESERVED VPRG AC PB HOT CC_AQC PRGC
R-00b R-0b R-0b R-0b R-0b R-0b R-0b
Table 7-8 INT1 Register Field Descriptions
Bit Field Type Reset Description
7-6 RESERVED R 00b
5 VPRG R 0b

Programming voltage interrupt:

0b = No significance.

1b = Input voltage is too low for programming power-up default values.

4 AC R 0b

AC_DET pin status change interrupt. Note: Status information is available in STATUS register.

0b = No change in status.

1b = AC_DET status change (AC_DET pin changed high to low or low to high).

3 PB R 0b

Push-button status change interrupt. Note: Status information is available in STATUS register

0b = No change in status.

1b = Push-button status change (PB changed high to low or low to high).

2 HOT R 0b

Thermal shutdown early warning:

0b = Chip temperature is below HOT threshold.

1b = Chip temperature exceeds HOT threshold.

1 CC_AQC R 0b

Coin cell battery voltage acquisition complete interrupt:

0b = No significance.

1b = Backup battery status comparators have settled and results are available in STATUS register.

0 PRGC R 0b

EEPROM programming complete interrupt:

0b = No significance.

1b = Programming of power-up default settings has completed successfully.

7.5.7 INT2 Register (subaddress = 0x02) [reset = 0x00]

INT2 is shown in Figure 7-38 and described in Table 7-9.

Return to Summary Table.

Figure 7-38 INT2 Register
7 6 5 4 3 2 1 0
RESERVED LS3_F LS2_F LS1_F LS3_I LS2_I LS1_I
R-00b R-0b R-0b R-0b R-0b R-0b R-0b
Table 7-9 INT2 Register Field Descriptions
Bit Field Type Reset Description
7-6 RESERVED R 00b
5 LS3_F R 0b

Load switch 3 fault interrupt:

0b = No fault. Switch is working normally.

1b = Load switch exceeded operating temperature limit and is temporarily disabled.

4 LS2_F R 0b

Load switch 2 fault interrupt:

0b = No fault. Switch is working normally.

1b = Load switch exceeded operating temperature limit or input voltage dropped below minimum value. Switch is temporarily disabled.

3 LS1_F R 0b

Load switch 1 fault interrupt:

0b = No fault. Switch is working normally.

1b = Load switch exceeded operating temperature limit and is temporarily disabled.

2 LS3_I R 0b

Load switch 3 current-limit interrupt:

0b = Load switch is disabled or not in current limit.

1b = Load switch is actively limiting the output current (output load is exceeding current limit value).

1 LS2_I R 0b

Load switch 2 current-limit interrupt:

0b = Load switch is disabled or not in current limit.

1b = Load switch is actively limiting the output current (output load is exceeding current limit value).

0 LS1_I R 0b

Load switch 1 current-limit interrupt:

0b = Load switch is disabled or not in current limit.

1b = Load switch is actively limiting the output current (output load is exceeding current limit value).

7.5.8 INT_MASK1 Register (subaddress = 0x03) [reset = 0x00]

INT_MASK1 is shown in Figure 7-39 and described in Table 7-10.

Return to Summary Table.

Figure 7-39 INT_MASK1 Register
7 6 5 4 3 2 1 0
RESERVED VPRGM ACM PBM HOTM CC_AQCM PRGCM
R-00b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b
Table 7-10 INT_MASK1 Register Field Descriptions
Bit Field Type Reset Description
7-6 RESERVED R 00b
5 VPRGM R/W 0b

Programming voltage interrupt mask bit. Note: mask bit has no effect on monitoring function:

0b = Interrupt is unmasked (interrupt event pulls nINT pin low).

1b = Interrupt is masked (interrupt has no effect on nINT pin).

4 ACM R/W 0b

AC_DET interrupt masking bit:

0b = Interrupt is unmasked (interrupt event pulls nINT pin low).

1b = Interrupt is masked (interrupt has no effect on nINT pin).

Note: mask bit has no effect on monitoring function.

3 PBM R/W 0b

PB interrupt masking bit. Note: mask bit has no effect on monitoring function.

0b = Interrupt is unmasked (interrupt event pulls nINT pin low).

1b = Interrupt is masked (interrupt has no effect on nINT pin).

2 HOTM R/W 0b

HOT interrupt masking bit. Note: mask bit has no effect on monitoring function.

0b = Interrupt is unmasked (interrupt event pulls nINT pin low).

1b = Interrupt is masked (interrupt has no effect on nINT pin).

1 CC_AQCM R/W 0b

C_AQC interrupt masking bit. Note: mask bit has no effect on monitoring function.

0b = Interrupt is unmasked (interrupt event pulls nINT pin low).

1b = Interrupt is masked (interrupt has no effect on nINT pin).

0 PRGCM R/W 0b

PRGC interrupt masking bit. Note: mask bit has no effect on monitoring function.

0b = Interrupt is unmasked (interrupt event pulls nINT pin low).

1b = Interrupt is masked (interrupt has no effect on nINT pin).

7.5.9 INT_MASK2 Register (subaddress = 0x04) [reset = 0x00]

INT_MASK2 is shown in Figure 7-40 and described in Table 7-11.

Return to Summary Table.

Figure 7-40 INT_MASK2 Register
7 6 5 4 3 2 1 0
RESERVED LS3_FM LS2_FM LS1_FM LS3_IM LS2_IM LS1_IM
R-00b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b
Table 7-11 INT_MASK2 Register Field Descriptions
Bit Field Type Reset Description
7-6 RESERVED R 00b
5 LS3_FM R/W 0b

LS3 fault interrupt mask bit. Note: mask bit has no effect on monitoring function.

0b = Interrupt is unmasked (interrupt event pulls nINT pin low).

1b = Interrupt is masked (interrupt has no effect on nINT pin).

4 LS2_FM R/W 0b

LS2 fault interrupt mask bit. Note: mask bit has no effect on monitoring function.

0b = Interrupt is unmasked (interrupt event pulls nINT pin low).

1b = Interrupt is masked (interrupt has no effect on nINT pin).

3 LS1_FM R/W 0b

LS1 fault interrupt mask bit. Note: mask bit has no effect on monitoring function.

0b = Interrupt is unmasked (interrupt event pulls nINT pin low).

1b = Interrupt is masked (interrupt has no effect on nINT pin).

2 LS3_IM R/W 0b

LS3 current-limit interrupt mask bit. Note: mask bit has no effect on monitoring function.

0b = Interrupt is unmasked (interrupt event pulls nINT pin low).

1b = Interrupt is masked (interrupt has no effect on nINT pin).

1 LS2_IM R/W 0b

LS2 current-limit interrupt mask bit. Note: mask bit has no effect on monitoring function.

0b = Interrupt is unmasked (interrupt event pulls nINT pin low).

1b = Interrupt is masked (interrupt has no effect on nINT pin).

0 LS1_IM R/W 0b

LS1 current-limit interrupt mask bit. Note: mask bit has no effect on monitoring function.

0b = Interrupt is unmasked (interrupt event pulls nINT pin low).

1b = Interrupt is masked (interrupt has no effect on nINT pin).

7.5.10 STATUS Register (subaddress = 0x05) [reset = 00XXXXXXb]

Register mask: C0h

STATUS is shown in Figure 7-41 and is described in Table 7-12.

Return to Summary Table.

Figure 7-41 STATUS Register
7 6 5 4 3 2 1 0
FSEAL EE AC_STATE PB_STATE STATE CC_STAT
R-0b R-0b R-X R-X R-X R-X
Table 7-12 STATUS Register Field Descriptions
Bit Field Type Reset Description
7 FSEAL R 0b

Freshness seal (FSEAL) status. Note: See Section 7.5.2 for details.

0b = FSEAL is in native state (fresh).

1b = FSEAL is broken.

6 EE R 0b

EEPROM status:

0b = EEPROM values have not been changed from factory default setting.

1b = EEPROM values have been changed from factory default settings.

5 AC_STATE R X

AC_DET input status bit:

0b = AC_DET input is inactive (AC_DET input pin is high).

1b = AC_DET input is active (AC_DET input is low).

4 PB_STATE R X

PB input status bit:

0b = Push Button input is inactive (PB input pin is high).

1b = Push Button input is active (PB input pin is low).

3-2 STATE R X

State machine STATE indication:

0h = PMIC is in transitional state.

1h = PMIC is in WAIT_PWR_EN state.

2h = PMIC is in ACTIVE state.

3h = PMIC is in SUSPEND state.

1-0 CC_STAT R X

Coin cell state of charge. Note: Coin-cell voltage acquisition must be triggered first before status bits are valid. See CC_AQ bit in Section 7.5.11.

0h = VCC < VLOW_LEVEL; Coin cell is not present or approaching end-of-life (EOL).

1h = VLOW_LEVEL < VCC < VGOOD_LEVEL; Coin cell voltage is LOW.

2h = VGOOD_LEVEL < VCC <VIDEAL_LEVEL; Coin cell voltage is GOOD.

3h = VIDEAL < VCC; Coin cell voltage is IDEAL.

7.5.11 CONTROL Register (subaddress = 0x06) [reset = 0x00]

CONTROL is shown in Figure 7-42 and described in Table 7-13.

Return to Summary Table.

Figure 7-42 CONTROL Register
7 6 5 4 3 2 1 0
RESERVED OFFnPFO CC_AQ
R-0000 00b R/W-0b R/W-0b
Table 7-13 CONTROL Register Field Descriptions
Bit Field Type Reset Description
7-2 RESERVED R 0000 00b
1 OFFnPFO R/W 0b

Power-fail shutdown bit:

0b = nPFO has no effect on PMIC state.

1b = All rails are shut down and PMIC enters OFF state when PFI comparator trips (nPFO is low).

0 CC_AQ R/W 0b

Coin Cell battery voltage acquisition start bit:

0b = No significance

1b = Triggers voltage acquisition. Bit is automatically reset to 0.

7.5.12 FLAG Register (subaddress = 0x07) [reset = 0x00]

FLAG is shown in Figure 7-43 and described in Table 7-14.

Return to Summary Table.

Figure 7-43 FLAG Register
7 6 5 4 3 2 1 0
GPO3_FLG GPO2_FLG GPO1_FLG LDO1_FLG DC4_FLG DC3_FLG DC2_FLG DC1_FLG
R-0b R-0b R-0b R-0b R-0b R-0b R-0b R-0b
Table 7-14 FLAG Register Field Descriptions
Bit Field Type Reset Description
7 GPO3_FLG R 0b

GPO3 Flag bit:

0b = Device powered up from OFF or SUSPEND state and GPO3 was disabled while in SUSPEND.

1b = Device powered up from SUSPEND state and GPO3 was enabled while in SUSPEND.

6 GPO2_FLG R 0b

GPO2 Flag bit

0b = Device powered up from OFF or SUSPEND state and GPO2 was disabled while in SUSPEND.

1b = Device powered up from SUSPEND state and GPO2 was enabled while in SUSPEND.

5 GPO1_FLG R 0b

GPO1 Flag bit:

0b = Device powered up from OFF or SUSPEND state and GPO1 was disabled while in SUSPEND.

1b = Device powered up from SUSPEND state and GPO1 was enabled while in SUSPEND.

4 LDO1_FLG R 0b

LDO1 Flag bit:

0b = Device powered up from OFF or SUSPEND state and LDO1 was disabled while in SUSPEND.

1b = Device powered up from SUSPEND state and LDO1 was enabled while in SUSPEND.

3 DC4_FLG R 0b

DCDC4 Flag bit:

0b = Device powered up from OFF or SUSPEND state and DCDC4 was disabled while in SUSPEND.

1b = Device powered up from SUSPEND state and DCDC4 was enabled while in SUSPEND.

2 DC3_FLG R 0b

DCDC3 Flag bit:

0b = Device powered up from OFF or SUSPEND state and DCDC3 was disabled while in SUSPEND.

1b = Device powered up from SUSPEND state and DCDC3 was enabled while in SUSPEND.

1 DC2_FLG R 0b

DCDC2 Flag bit:

0b = Device powered up from OFF or SUSPEND state and DCDC2 was disabled while in SUSPEND.

1b = Device powered up from SUSPEND state and DCDC2 was enabled while in SUSPEND.

0 DC1_FLG R 0b

DCDC1 Flag bit:

0b = Device powered up from OFF or SUSPEND state and DCDC1 was disabled while in SUSPEND.

1b = Device powered up from SUSPEND state and GDCDC1PO3 was enabled while in SUSPEND.

7.5.13 PASSWORD Register (subaddress = 0x10) [reset = 0x00]

PASSWORD is shown in Figure 7-44 and described in Table 7-15.

Return to Summary Table.

Figure 7-44 PASSWORD Register
7 6 5 4 3 2 1 0
PWRD
R/W-00h
Table 7-15 PASSWORD Register Field Descriptions
Bit Field Type Reset Description
7-0 PWRD R/W 00h

Register is used for accessing password protected registers (see Section 7.5.1 for details). Breaking the freshness seal (see Section 7.5.2 for details). Programming power-up default values . Read-back always yields 0x00.

7.5.14 ENABLE1 Register (subaddress = 0x11) [reset = 0x00]

ENABLE1 is shown in Figure 7-45 and described in Table 7-16.

Return to Summary Table.

Password protected.

Figure 7-45 ENABLE1 Register
7 6 5 4 3 2 1 0
RESERVED DC6_EN DC5_EN DC4_EN DC3_EN DC2_EN DC1_EN
R-00b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b
Table 7-16 ENABLE1 Register Field Descriptions
Bit Field Type Reset Description
7-6 RESERVED R 00b
5 DC6_EN R/W 0b

DCDC6 enable bit. DCDC6 can only be disabled if FSEAL = 0. See Section 7.5.2 for details.

0b = Disabled

1b = Enabled

4 DC5_EN R/W 0b

DCDC5 enable bit. Note: At power-up and down this bit is automatically updated by the internal power sequencer. DCDC5 can only be disabled if FSEAL = 0. See Section 7.5.2 for details.

0b = Disabled

1b = Enabled

3 DC4_EN R/W 0b

DCDC4 enable bit. Note: At power-up and down this bit is automatically updated by the internal power sequencer.

0b = Disabled

1b = Enabled

2 DC3_EN R/W 0b

DCDC3 enable bit. Note: At power-up and down this bit is automatically updated by the internal power sequencer.

0b = Disabled

1b = Enabled

1 DC2_EN R/W 0b

DCDC2 enable bit. Note: At power-up and down this bit is automatically updated by the internal power sequencer.

0b = Disabled

1b = Enabled

0 DC1_EN R/W 0b

DCDC1 enable bit. Note: At power-up and down this bit is automatically updated by the internal power sequencer.

0b = Disabled

1b = Enabled

7.5.15 ENABLE2 Register (subaddress = 0x12) [reset = 0x00]

ENABLE2 is shown in Figure 7-46 and described in Table 7-17.

Return to Summary Table.

Password protected.

Figure 7-46 ENABLE2 Register
7 6 5 4 3 2 1 0
RESERVED GPIO3 GPIO2 GPIO1 LS3_EN LS2_EN LS1_EN LDO1_EN
R-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b
Table 7-17 ENABLE2 Register Field Descriptions
Bit Field Type Reset Description
7 RESERVED R 0b
6 GPIO3 R/W 0b

General purpose output 3 / reset polarity. Note: If DC12_RST bit (register 0x14) is set to 1 this bit has no function.

0b = GPIO3 output is driven low.

1b = GPIO3 output is HiZ.

5 GPIO2 R/W 0b

General purpose output 2. Note: If IO_SEL bit (register 0x13) is set to 1 this bit has no function.

0b = GPO2 output is driven low.

1b = GPO2 output is HiZ.

4 GPIO1 R/W 0b

General purpose output 1. Note: If IO_SEL bit (register 0x13) is set to 1 this bit has no function.

0b = GPO1 output is driven low.

1b = GPO1 output is HiZ.

3 LS3_EN R/W 0b

Load switch 3 (LS3) enable bit.

0b = Disabled

1b = Enabled

2 LS2_EN R/W 0b

Load switch 2 (LS2) enable bit.

0b = Disabled

1b = Enabled

1 LS1_EN R/W 0b

Load switch 1 (LS1) enable bit.

0b = Disabled

1b = Enabled

Note: At power-up and down this bit is automatically updated by the internal power sequencer.

0 LDO1_EN R/W 0b

LDO1 enable bit.

0b = Disabled

1b = Enabled

Note: At power-up and down this bit is automatically updated by the internal power sequencer.

7.5.16 CONFIG1 Register (subaddress = 0x13) [reset = 0x08]

CONFIG1 is shown in Figure 7-47 and described in Table 7-18.

Return to Summary Table.

Password protected.

Figure 7-47 CONFIG1 Register
7 6 5 4 3 2 1 0
TRST GPO2_BUF IO1_SEL PGDLY STRICT UVLO
R/W-0b R/W-0b R/W-0b R/W-01b R/W-0b R/W-00b
Table 7-18 CONFIG1 Register Field Descriptions
Bit Field Type Reset Description
7 TRST R/W 0b

Push-button reset time constant:

0b = 8 s

1b = 15 s

6 GPO2_BUF R/W 0b

GPO2 output buffer configuration:

0b = GPO2 buffer is configured as open-drain.

1b = GPO2 buffer is configured as push-pull (high-level is driven to IN_LS1).

5 IO1_SEL R/W 0b

GPIO1 / GPO2 configuration bit. See Section 7.3.1.14 for details.

0b = GPIO1 is configured as general-purpose, open-drain output. GPO2 is independent output.

1b = GPIO1 is configured as input, controlling GPO2. Intended for DDR3 reset signal control.

4-3 PGDLY R/W 01b

Power-Good delay. Note: Power-good delay applies to rising-edge only (power-up), not falling edge (power-down or fault).

00b = 10 ms

01b = 20 ms

10b = 50 ms

11b = 150 ms

2 STRICT R/W 0b

Supply Voltage Supervisor Sensitivity selection. See Section 6.5 for details.

0b = Power-good threshold (VOUT falling) has wider limits. Over-voltage is not monitored.

1b = Power-good threshold (VOUT falling) has tight limits. Over-voltage is monitored.

1-0 UVLO R/W 00b

UVLO setting

00b = 2.75 V

01b = 2.95 V

10b = 3.25 V

11b = 3.35 V

7.5.17 CONFIG2 Register (subaddress = 0x14) [reset = 0x40]

CONFIG2 is shown in Figure 7-48 and described in Table 7-19.

Return to Summary Table.

Password protected.

Figure 7-48 CONFIG2 Register
7 6 5 4 3 2 1 0
DC12_RST UVLOHYS RESERVED LS3ILIM LS2ILIM
R/W-0b R/W-1b R-00b R/W-00b R/W-00b
Table 7-19 CONFIG2 Register Field Descriptions
Bit Field Type Reset Description
7 DC12_RST R/W 0b

DCDC1 and DCDC2 reset-pin enable:

0b = GPIO3 is configured as general-purpose output.

1b = GPIO3 is configured as warm-reset input to DCDC1 and DCDC2.

6 UVLOHYS R/W 1b

UVLO hysteresis:

0b = 200 mV

1b = 400 mV

5-4 RESERVED R 00b
3-2 LS3ILIM R/W 00b

Load switch 3 (LS3) current limit selection:

00b = 100 mA, (MIN = 98 mA)

01b = 200 mA, (MIN = 194 mA)

10b = 500 mA, (MIN = 475 mA)

11b = 1000 mA, (MIN = 900 mA)

See the LS3 current limit specification in for more details.

1-0 LS2ILIM R/W 00b

Load switch 2 (LS2) current limit selection:

00b = 100 mA, (MIN = 94 mA)

01b = 200 mA, (MIN = 188 mA)

10b = 500 mA, (MIN = 465 mA)

11b = 1000 mA, (MIN = 922 mA)

See the LS2 current limit specification in for more details.

7.5.18 CONFIG3 Register (subaddress = 0x15) [reset = 0x0]

CONFIG3 is shown in Figure 7-49 and described in Table 7-20.

Return to Summary Table.

Password protected.

Figure 7-49 CONFIG3 Register
7 6 5 4 3 2 1 0
RESERVED LS3nPFO LS2nPFO LS1nPFO LS3DCHRG LS2DCHRG LS1DCHRG
R-00b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b
Table 7-20 CONFIG3 Register Field Descriptions
Bit Field Type Reset Description
7-6 RESERVED R 00b
5 LS3nPFO R/W 0b

Load switch 3 power-fail disable bit:

0b = Load switch status is not affected by power-fail comparator.

1b = Load switch is disabled if power-fail comparator trips (nPFO is low).

4 LS2nPFO R/W 0b

Load switch 2 power-fail disable bit:

0b = Load switch status is not affected by power-fail comparator.

1b = Load switch is disabled if power-fail comparator trips (nPFO is low).

3 LS1nPFO R/W 0b

Load switch 1 power-fail disable bit:

0b = Load switch status is not affected by power-fail comparator.

1b = Load switch is disabled if power-fail comparator trips (nPFO is low).

2 LS3DCHRG R/W 0b

Load switch 3 discharge enable bit:

0b = Active discharge is disabled.

1b = Active discharge is enabled (load switch output is actively discharged when switch is OFF).

1 LS2DCHRG R/W 0b

Load switch 2 discharge enable bit:

0b = Active discharge is disabled.

1b = Active discharge is enabled (load switch output is actively discharged when switch is OFF).

0 LS1DCHRG R/W 0b

Load switch 1 discharge enable bit:

0b = Active discharge is disabled.

1b = Active discharge is enabled (load switch output is actively discharged when switch is OFF).

7.5.19 DCDC1 Register (offset = 0x16) [reset = 0xB5]

DCDC1 is shown in Figure 7-50 and described in Table 7-21.

Return to Summary Table.

Note 1: This register is password protected. For more information, see Section 7.5.1.
Note 2: A 5-ms blanking time of the over-voltage and under-voltage monitoring occurs when a write is performed on the DCDC1 register.
Note 3: To change the output voltage of DCDC1, the GO bit or the GODSBL bit must be set to 1b in register 0x1A.

Figure 7-50 DCDC1 Register
7 6 5 4 3 2 1 0
PFM RESERVED DCDC1
R/W-1b R-0b R/W-35h
Table 7-21 DCDC1 Register Field Descriptions
Bit Field Type Reset Description
7 PFM R/W 1b

Pulse Frequency Modulation (PFM, also known as pulse-skip-mode) enable. PFM mode improves light-load efficiency. Actual PFM mode operation depends on load condition.

0b = Disabled (forced PWM)

1b = Enabled

6 RESERVED R 0b
5-0 DCDC1 R/W 35h

DCDC1 output voltage setting:

0h = 0.850

1h = 0.860

2h = 0.870

3h = 0.880

4h = 0.890

5h = 0.900

6h = 0.910

7h = 0.920

8h = 0.930

9h = 0.940

Ah = 0.950

Bh = 0.960

Ch = 0.970

Dh = 0.980

Eh = 0.990

Fh = 1.000

10h = 1.010

11h = 1.020

12h = 1.030

13h = 1.040

14h = 1.050

15h = 1.060

16h = 1.070

17h = 1.080

18h = 1.090

19h = 1.100

1Ah = 1.110

1Bh = 1.120

1Ch = 1.130

1Dh = 1.140

1Eh = 1.150

1Fh = 1.160

20h = 1.170

21h = 1.180

22h = 1.190

23h = 1.200

24h = 1.210

25h = 1.220

26h = 1.230

27h = 1.240

28h = 1.250

29h = 1.260

2Ah = 1.270

2Bh = 1.280

2Ch = 1.290

2Dh = 1.300

2Eh = 1.310

2Fh = 1.320

30h = 1.330

31h = 1.340

32h = 1.350

33h = 1.375

34h = 1.400

35h = 1.425

36h = 1.450

37h = 1.475

38h = 1.500

39h = 1.525

3Ah = 1.550

3Bh = 1.575

3Ch = 1.600

3Dh = 1.625

3Eh = 1.650

3Fh = 1.675

7.5.20 DCDC2 Register (subaddress = 0x17) [reset = 0xB5]

DCDC2 is shown in Figure 7-51 and described in Table 7-22.

Return to Summary Table.

Note 1: This register is password protected. For more information, see Section 7.5.1.
Note 2: A 5-ms blanking time of the over-voltage and under-voltage monitoring occurs when a write is performed on the DCDC2 register.
Note 3: To change the output voltage of DCDC2, the GO bit or the GODSBL bit must be set to 1b in register 0x1A.

Figure 7-51 DCDC2 Register
7 6 5 4 3 2 1 0
PFM RESERVED DCDC2
R/W-1b R-0b R/W-35h
Table 7-22 DCDC2 Register Field Descriptions
Bit Field Type Reset Description
7 PFM R/W 1b

Pulse frequency modulation (PFM, also known as pulse-skip-mode) enable. PFM mode improves light-load efficiency. Actual PFM mode operation depends on load condition.

0b = Disabled (forced PWM)

1b = Enabled

6 RESERVED R 0b
5-0 DCDC2 R/W 35h

DCDC2 output voltage setting:

0h = 0.850

1h = 0.860

2h = 0.870

3h = 0.880

4h = 0.890

5h = 0.900

6h = 0.910

7h = 0.920

8h = 0.930

9h = 0.940

Ah = 0.950

Bh = 0.960

Ch = 0.970

Dh = 0.980

Eh = 0.990

Fh = 1.000

10h = 1.010

11h = 1.020

12h = 1.030

13h = 1.040

14h = 1.050

15h = 1.060

16h = 1.070

17h = 1.080

18h = 1.090

19h = 1.100

1Ah = 1.110

1Bh = 1.120

1Ch = 1.130

1Dh = 1.140

1Eh = 1.150

1Fh = 1.160

20h = 1.170

21h = 1.180

22h = 1.190

23h = 1.200

24h = 1.210

25h = 1.220

26h = 1.230

27h = 1.240

28h = 1.250

29h = 1.260

2Ah = 1.270

2Bh = 1.280

2Ch = 1.290

2Dh = 1.300

2Eh = 1.310

2Fh = 1.320

30h = 1.330

31h = 1.340

32h = 1.350

33h = 1.375

34h = 1.400

35h = 1.425

36h = 1.450

37h = 1.475

38h = 1.500

39h = 1.525

3Ah = 1.550

3Bh = 1.575

3Ch = 1.600

3Dh = 1.625

3Eh = 1.650

3Fh = 1.675

7.5.21 DCDC3 Register (subaddress = 0x18) [reset = 0x98]

DCDC3 is shown in Figure 7-52 and described in Table 7-23.

Return to Summary Table.

Note 1: This register is password protected. For more information, see Section 7.5.1.
Note 2: A 5-ms blanking time of the over-voltage and under-voltage monitoring occurs when a write is performed on the DCDC3 register.

Note:

Power-up default may differ depending on RSEL value. See Section 7.3.1.13 for details.

Figure 7-52 DCDC3 Register
7 6 5 4 3 2 1 0
PFM RESERVED DCDC3
R/W-1b R-0b R/W-18h
Table 7-23 DCDC3 Register Field Descriptions
Bit Field Type Reset Description
7 PFM R/W 1b

Pulse Frequency Modulation (PFM, also known as pulse-skip-mode) enable. PFM mode improves light-load efficiency. Actual PFM mode operation depends on load condition.

0b = Disabled (forced PWM)

1b = Enabled

6 RESERVED R 0b
5-0 DCDC3 R/W 18h

DCDC3 output voltage setting:

0h = 0.900

1h = 0.925

2h = 0.950

3h = 0.975

4h = 1.000

5h = 1.025

6h = 1.050

7h = 1.075

8h = 1.100

9h = 1.125

Ah = 1.150

Bh = 1.175

Ch = 1.200

Dh = 1.225

Eh = 1.250

Fh = 1.275

10h = 1.300

11h = 1.325

12h = 1.350

13h = 1.375

14h = 1.400

15h = 1.425

16h = 1.450

17h = 1.475

18h = 1.500

19h = 1.525

1Ah = 1.550

1Bh = 1.600

1Ch = 1.650

1Dh = 1.700

1Eh = 1.750

1Fh = 1.800

20h = 1.850

21h = 1.900

22h = 1.950

23h = 2.000

24h = 2.050

25h = 2.100

26h = 2.150

27h = 2.200

28h = 2.250

29h = 2.300

2Ah = 2.350

2Bh = 2.400

2Ch = 2.450

2Dh = 2.500

2Eh = 2.550

2Fh = 2.600

30h = 2.650

31h = 2.700

32h = 2.750

33h = 2.800

34h = 2.850

35h = 2.900

36h = 2.950

37h = 3.000

38h = 3.050

39h = 3.100

3Ah = 3.150

3Bh = 3.200

3Ch = 3.250

3Dh = 3.300

3Eh = 3.350

3Fh = 3.400

7.5.22 DCDC4 Register (subaddress = 0x19) [reset = 0xB2]

DCDC4 is shown in Figure 7-53 and described in Table 7-24.

Return to Summary Table.

Note 1: This register is password protected. For more information, see Section 7.5.1.
Note 2: A 5-ms blanking time of the over-voltage and under-voltage monitoring occurs when a write is performed on the DCDC4 register.

Note:

Power-up default may differ depending on RSEL value. See Section 7.3.1.13 for details. The Reserved setting should not be selected and the output voltage settings should not be modified while the converter is operating.

Figure 7-53 DCDC4 Register
7 6 5 4 3 2 1 0
PFM RESERVED DCDC4
R/W-1b R-0b R/W-32h
Table 7-24 DCDC4 Register Field Descriptions
Bit Field Type Reset Description
7 PFM R/W 1b

Pulse Frequency Modulation (PFM, also known as pulse-skip-mode) enable. PFM mode improves light-load efficiency. Actual PFM mode operation depends on load condition.

0b = Disabled (forced PWM)

1b = Enabled

6 RESERVED R 0b
5-0 DCDC4 R/W 32h

DCDC4 output voltage setting:

0h = 1.175

1h = 1.200

2h = 1.225

3h = 1.250

4h = 1.275

5h = 1.300

6h = 1.325

7h = 1.350

8h = 1.375

9h = 1.400

Ah = 1.425

Bh = 1.450

Ch = 1.475

Dh = 1.500

Eh = 1.525

Fh = 1.550

10h = 1.600

11h = 1.650

12h = 1.700

13h = 1.750

14h = 1.800

15h = 1.850

16h = 1.900

17h = 1.950

18h = 2.000

19h = 2.050

1Ah = 2.100

1Bh = 2.150

1Ch = 2.200

1Dh = 2.250

1Eh = 2.300

1Fh = 2.3500

20h = 2.400

21h = 2.450

22h = 2.500

23h = 2.550

24h = 2.600

25h = 2.650

26h = 2.700

27h = 2.750

28h = 2.800

29h = 2.850

2Ah = 2.900

2Bh = 2.950

2Ch = 3.000

2Dh = 3.050

2Eh = 3.100

2Fh = 3.150

30h = 3.200

31h = 3.250

32h = 3.300

33h = 3.350

34h = 3.400

35h = reserved

36h = reserved

37h = reserved

38h = reserved

39h = reserved

3Ah = reserved

3Bh = reserved

3Ch = reserved

3Dh = reserved

3Eh = reserved

3Fh = reserved

7.5.23 SLEW Register (subaddress = 0x1A) [reset = 0x06]

SLEW is shown in Figure 7-54 and described in Table 7-25.

Return to Summary Table.

Note:

Slew-rate control applies to DCDC1 and DCDC2 only. If changing from a higher voltage to lower voltage while STRICT = 1 and converters are in a no load state, PFM bit for DCDC1 and DCDC2 must be set to 0.

Figure 7-54 SLEW Register
7 6 5 4 3 2 1 0
GO GODSBL RESERVED SLEW
R/W-0b R/W-0b R-000b R/W-6h
Table 7-25 SLEW Register Field Descriptions
Bit Field Type Reset Description
7 GO R/W 0b

Go bit. Note: Bit is automatically reset at the end of the voltage transition.

0b = No change

1b = Initiates the transition from present state to the output voltage setting currently stored in DCDC1 and DCDC2 register. SLEW setting does apply.

6 GODSBL R/W 0b

Go disable bit

0b = Enabled

1b = Disabled; DCDC1 and DCDC2 output voltage changes whenever set-point is updated in DCDC1 and DCDC2 register without having to write to the GO bit. SLEW setting does apply.

5-3 RESERVED R 000b
2-0 SLEW R/W 6h

Output slew rate setting:

0h = 160 µs/step (0.0625 mV/µs at 10 mV per step)

1h = 80 µs/step (0.125 mV/µs at 10 mV per step)

2h = 40 µs/step (0.250 mV/µs at 10 mV per step)

3h = 20 µs/step (0.500 mV/µs at 10 mV per step)

4h = 10 µs/step (1.0 mV/µs at 10 mV per step)

5h = 5 µs/step (2.0 mV/µs at 10 mV per step)

6h = 2.5 µs/step (4.0 mV/µs at 10 mV per step)

7h = Immediate; slew rate is only limited by control loop response time. Note: The actual slew rate depends on the voltage step per code. Refer to DCDCx registers for details.

7.5.24 LDO1 Register (subaddress = 0x1B) [reset = 0x1F]

LDO1 is shown in Figure 7-55 and described in Table 7-26.

Return to Summary Table.

Note 1: This register is password protected. For more information, see Section 7.5.1.
Note 2: A 5-ms blanking time of the over-voltage and under-voltage monitoring occurs when a write is performed on the LDO1 register.

Figure 7-55 LDO1 Register
7 6 5 4 3 2 1 0
RESERVED LDO1
R-00b R/W-1Fh
Table 7-26 LDO1 Register Field Descriptions
Bit Field Type Reset Description
7-6 RESERVED R 00b
5-0 LDO1 R/W 1Fh

LDO1 output voltage setting:

0h = 0.900

1h = 0.925

2h = 0.950

3h = 0.975

4h = 1.000

5h = 1.025

6h = 1.050

7h = 1.075

8h = 1.100

9h = 1.125

Ah = 1.150

Bh = 1.175

Ch = 1.200

Dh = 1.225

Eh = 1.250

Fh = 1.275

10h = 1.300

11h = 1.325

12h = 1.350

13h = 1.375

14h = 1.400

15h = 1.425

16h = 1.450

17h = 1.475

18h = 1.500

19h = 1.525

1Ah = 1.550

1Bh = 1.600

1Ch = 1.650

1Dh = 1.700

1Eh = 1.750

1Fh = 1.800

20h = 1.850

21h = 1.900

22h = 1.950

23h = 2.000

24h = 2.050

25h = 2.100

26h = 2.150

27h = 2.200

28h = 2.250

29h = 2.300

2Ah = 2.350

2Bh = 2.400

2Ch = 2.450

2Dh = 2.500

2Eh = 2.550

2Fh = 2.600

30h = 2.650

31h = 2.700

32h = 2.750

33h = 2.800

34h = 2.850

35h = 2.900

36h = 2.950

37h = 3.000

38h = 3.050

39h = 3.100

3Ah = 3.150

3Bh = 3.200

3Ch = 3.250

3Dh = 3.300

3Eh = 3.350

3Fh = 3.400

7.5.25 SEQ1 Register (subaddress = 0x20) [reset = 0x00]

SEQ1 is shown in Figure 7-56 and described in Table 7-27.

Return to Summary Table.

Password protected.

Figure 7-56 SEQ1 Register
7 6 5 4 3 2 1 0
DLY8 DLY7 DLY6 DLY5 DLY4 DLY3 DLY2 DLY1
R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b
Table 7-27 SEQ1 Register Field Descriptions
Bit Field Type Reset Description
7 DLY8 R/W 0b

Delay8 (occurs after Strobe 8 and before Strobe 9.)

0b = 2 ms

1b = 5 ms

6 DLY7 R/W 0b

Delay7 (occurs after Strobe 7 and before Strobe 8.)

0b = 2 ms

1b = 5 ms

5 DLY6 R/W 0b

Delay6 (occurs after Strobe 6 and before Strobe 7.)

0b = 2 ms

1b = 5 ms

4 DLY5 R/W 0b

Delay5 (occurs after Strobe 5 and before Strobe 6.)

0b = 2 ms

1b = 5 ms

3 DLY4 R/W 0b

Delay4 (occurs after Strobe 4 and before Strobe 5.)

0b = 2 ms

1b = 5 ms

2 DLY3 R/W

0b

Delay3 (occurs after Strobe 3 and before Strobe 4.)

0b = 2 ms

1b = 5 ms

1 DLY2 R/W

0b

Delay2 (occurs after Strobe 2 and before Strobe 3.)

0b = 2 ms

1b = 5 ms

0 DLY1 R/W 0b

Delay1 (occurs after Strobe 1 and before Strobe 2.)

0b = 2 ms

1b = 5 ms

7.5.26 SEQ2 Register (subaddress = 0x21) [reset = 0x00]

SEQ2 is shown in Figure 7-57 and described in Table 7-28.

Return to Summary Table.

Password protected.

Figure 7-57 SEQ2 Register
7 6 5 4 3 2 1 0
DLYFCTR RESERVED DLY9
R/W -0b R-000 000b R/W -0b
Table 7-28 SEQ2 Register Field Descriptions
Bit Field Type Reset Description
7 DLYFCTR R/W 0b

Power-down delay factor:

0b = 1x

1b = 10x (delay times are multiplied by 10x during power-down.)

Note: DLYFCTR has no effect on power-up timing.

6-1 RESERVED R 000 000b
0 DLY9 R/W 0b

Delay9 (occurs after Strobe 9 and before Strobe 10.)

0b = 2 ms

1b = 5 ms

7.5.27 SEQ3 Register (subaddress = 0x22)[reset = 0x55]

SEQ3 is shown in Figure 7-58 and described in Table 7-29.

Return to Summary Table.

Password protected.

Figure 7-58 SEQ3 Register
7 6 5 4 3 2 1 0
DC2_SEQ DC1_SEQ
R/W-5h R/W-5h
Table 7-29 SEQ3 Register Field Descriptions
Bit Field Type Reset Description
7-4 DC2_SEQ R/W 5h

DCDC2 enable STROBE:

0h = Rail is not controlled by sequencer.

1h = Rail is not controlled by sequencer.

2h = Rail is not controlled by sequencer.

3h = Enable at STROBE 3.

4h = Enable at STROBE 4.

5h = Enable at STROBE 5.

6h = Enable at STROBE 6.

7h = Enable at STROBE 7.

8h = Enable at STROBE 8.

9h = Enable at STROBE 9.

Ah = Enable at STROBE 10.

Bh = Rail is not controlled by sequencer.

Ch = Rail is not controlled by sequencer.

Dh = Rail is not controlled by sequencer.

Eh = Rail is not controlled by sequencer.

Fh = Rail is not controlled by sequencer.

3-0 DC1_SEQ R/W 5h

DCDC1 enable STROBE:

0h = Rail is not controlled by sequencer.

1h = Rail is not controlled by sequencer.

2h = Rail is not controlled by sequencer.

3h = Enable at STROBE 3.

4h = Enable at STROBE 4.

5h = Enable at STROBE 5.

6h = Enable at STROBE 6.

7h = Enable at STROBE 7.

8h = Enable at STROBE 8.

9h = Enable at STROBE 9.

Ah = Enable at STROBE 10.

Bh = Rail is not controlled by sequencer.

Ch = Rail is not controlled by sequencer.

Dh = Rail is not controlled by sequencer.

Eh = Rail is not controlled by sequencer.

Fh = Rail is not controlled by sequencer.

7.5.28 SEQ4 Register (subaddress = 0x23) [reset = 0x37]

SEQ4 is shown in Figure 7-59 and described in Table 7-30.

Return to Summary Table.

Password protected.

Figure 7-59 SEQ4 Register
7 6 5 4 3 2 1 0
DC4_SEQ DC3_SEQ
R/W-3h R/W-7h
Table 7-30 SEQ4 Register Field Descriptions
Bit Field Type Reset Description
7-4 DC4_SEQ R/W 3h

DCDC4 enable STROBE:

0h = Rail is not controlled by sequencer.

1h = Rail is not controlled by sequencer.

2h = Rail is not controlled by sequencer.

3h = Enable at STROBE 3.

4h = Enable at STROBE 4.

5h = Enable at STROBE 5.

6h = Enable at STROBE 6.

7h = Enable at STROBE 7.

8h = Enable at STROBE 8.

9h = Enable at STROBE 9.

Ah = Enable at STROBE 10.

Bh = Rail is not controlled by sequencer.

Ch = Rail is not controlled by sequencer.

Dh = Rail is not controlled by sequencer.

Eh = Rail is not controlled by sequencer.

Fh = Rail is not controlled by sequencer.

3-0 DC3_SEQ R/W 7h

DCDC3 enable STROBE:

0h = Rail is not controlled by sequencer.

1h = Rail is not controlled by sequencer.

2h = Rail is not controlled by sequencer.

3h = Enable at STROBE 3.

4h = Enable at STROBE 4.

5h = Enable at STROBE 5.

6h = Enable at STROBE 6.

7h = Enable at STROBE 7.

8h = Enable at STROBE 8.

9h = Enable at STROBE 9.

Ah = Enable at STROBE 10.

Bh = Rail is not controlled by sequencer.

Ch = Rail is not controlled by sequencer.

Dh = Rail is not controlled by sequencer.

Eh = Rail is not controlled by sequencer.

Fh = Rail is not controlled by sequencer.

7.5.29 SEQ5 Register (subaddress = 0x24) [reset = 0x00]

SEQ5 is shown in Figure 7-60 and described in Table 7-31.

Return to Summary Table.

Password protected.

Figure 7-60 SEQ5 Register
7 6 5 4 3 2 1 0
RESERVED DC6_SEQ RESERVED DC5_SEQ
R-0h R/W-0h R-0h R/W-0h
Table 7-31 SEQ5 Register Field Descriptions
Bit Field Type Reset Description
7-6 RESERVED R 0h
5-4 DC6_SEQ R/W 0h

DCDC6 enable STROBE. Note: STROBE 1 and STROBE 2 are executed only if FSEAL = 0. DCDC5 and 6 cannot be disabled by sequencer once freshness seal is broken.

0h = Rail is not controlled by sequencer.

1h = Enable at STROBE 1.

2h = Enable at STROBE 2.

3h = Rail is not controlled by sequencer.

3-2 RESERVED R 0h
1-0 DC5_SEQ R/W 0h

DCDC5 enable STROBE. Note: STROBE 1 and STROBE 2 are executed only if FSEAL = 0. DCDC5 and 6 cannot be disabled by sequencer once freshness seal is broken.

0h = Rail is not controlled by sequencer.

1h = Enable at STROBE 1.

2h = Enable at STROBE 2.

3h = Rail is not controlled by sequencer.

7.5.30 SEQ6 Register (subaddress = 0x25) [reset = 0xA8]

SEQ6 is shown in Figure 7-61 and described in Table 7-32.

Return to Summary Table.

Password protected.

Figure 7-61 SEQ6 Register
7 6 5 4 3 2 1 0
LS1_SEQ LDO1_SEQ
R/W-Ah R/W-8h
Table 7-32 SEQ6 Register Field Descriptions
Bit Field Type Reset Description
7-4 LS1_SEQ R/W Ah

LS1 enable STROBE:

0h = Rail is not controlled by sequencer.

1h = Rail is not controlled by sequencer.

2h = Rail is not controlled by sequencer.

3h = Enable at STROBE 3.

4h = Enable at STROBE 4.

5h = Enable at STROBE 5.

6h = Enable at STROBE 6.

7h = Enable at STROBE 7.

8h = Enable at STROBE 8.

9h = Enable at STROBE 9.

Ah = Enable at STROBE 10.

Bh = Rail is not controlled by sequencer.

Ch = Rail is not controlled by sequencer.

Dh = Rail is not controlled by sequencer.

Eh = Rail is not controlled by sequencer.

Fh = Rail is not controlled by sequencer.

3-0 LDO1_SEQ R/W 8h

LDO1 enable STROBE:

0h = Rail is not controlled by sequencer.

1h = Rail is not controlled by sequencer.

2h = Rail is not controlled by sequencer.

3h = Enable at STROBE 3.

4h = Enable at STROBE 4.

5h = Enable at STROBE 5.

6h = Enable at STROBE 6.

7h = Enable at STROBE 7.

8h = Enable at STROBE 8.

9h = Enable at STROBE 9.

Ah = Enable at STROBE 10.

Bh = Rail is not controlled by sequencer.

Ch = Rail is not controlled by sequencer.

Dh = Rail is not controlled by sequencer.

Eh = Rail is not controlled by sequencer.

Fh = Rail is not controlled by sequencer.

7.5.31 SEQ7 Register (subaddress = 0x26) [reset = 0x09]

SEQ7 is shown in Figure 7-62 and described in Table 7-33.

Return to Summary Table.

Password protected.

Figure 7-62 SEQ7 Register
7 6 5 4 3 2 1 0
GPO3_SEQ GPO1_SEQ
R/W-0h R/W-9h
Table 7-33 SEQ7 Register Field Descriptions
Bit Field Type Reset Description
7-4 GPO3_SEQ R/W

0h

GPO3 enable STROBE:

0h = Rail is not controlled by sequencer.

1h = Rail is not controlled by sequencer.

2h = Rail is not controlled by sequencer.

3h = Enable at STROBE 3.

4h = Enable at STROBE 4.

5h = Enable at STROBE 5.

6h = Enable at STROBE 6.

7h = Enable at STROBE 7.

8h = Enable at STROBE 8.

9h = Enable at STROBE 9.

Ah = Enable at STROBE 10.

Bh = Rail is not controlled by sequencer.

Ch = Rail is not controlled by sequencer.

Dh = Rail is not controlled by sequencer.

Eh = Rail is not controlled by sequencer.

Fh = Rail is not controlled by sequencer.

3-0 GPO1_SEQ R/W 9h

GPO1 enable STROBE:

0h = Rail is not controlled by sequencer.

1h = Rail is not controlled by sequencer.

2h = Rail is not controlled by sequencer.

3h = Enable at STROBE 3.

4h = Enable at STROBE 4.

5h = Enable at STROBE 5.

6h = Enable at STROBE 6.

7h = Enable at STROBE 7.

8h = Enable at STROBE 8.

9h = Enable at STROBE 9.

Ah = Enable at STROBE 10.

Bh = Rail is not controlled by sequencer.

Ch = Rail is not controlled by sequencer.

Dh = Rail is not controlled by sequencer.

Eh = Rail is not controlled by sequencer.

Fh = Rail is not controlled by sequencer.