SLVSBM4C September   2012  – January 2016 TPS717-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Internal Current Limit
      2. 7.3.2 Shutdown
      3. 7.3.3 Startup and Noise Reduction Capacitor
      4. 7.3.4 Undervoltage Lockout (UVLO)
      5. 7.3.5 Minimum Load
      6. 7.3.6 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Transient Response
      2. 8.1.2 Input and Output Capacitor Requirements
      3. 8.1.3 Dropout Voltage
      4. 8.1.4 Power Dissipation
      5. 8.1.5 Output Noise
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Design Considerations
        2. 8.2.2.2 Powering a PLL Integrated on an SOC
        3. 8.2.2.3 Design Considerations
      3. 8.2.3 Application Curve
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Module
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings

over operating temperature range (unless otherwise noted), all voltages are with respect to GND(1)
MIN MAX UNIT
Voltage VIN –0.3 7 V
VFB –0.3 3.6
VNR –0.3 3.6
VEN –0.3 VIN + 0.3 V(2)
VOUT –0.3 7
Current IOUT Internally limited A
Continuous total power dissipation PDISS See Thermal Information table
Ambient temperature TA –40 125 °C
Operating junction temperature TJ –55 150 °C
Storage temperature Tstg –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) VEN absolute maximum rating is VIN + 0.3 V or 7 V, whichever is greater.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) ±2000 V
TPS717-Q1 in DCK and DSE packages
V(ESD) Electrostatic discharge Charged device model (CDM), per AEC Q100-011 All pins ±750 V
Corner pins,
DCK (1, 3, 4, and 5)		 ±750
Corner pins,
DSE (1, 3, 4, and 6)		 ±750
TPS717-Q1 in DRV package
V(ESD) Electrostatic discharge Charged device model (CDM), per AEC Q100-011 All pins ±500 V
Corner pins (1, 3, 4, and 6) ±750
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN Input voltage 2.5 6.5 V
VOUT Output voltage 0.9 5 V
IOUT Output current 0 150 mA
VEN Enable voltage 0 VIN V
CIN Input capacitor 1 µF
R2 Lower feedback resistor 160 320 332 kΩ
CNR Noise reduction capacitor 10 nF
COUT Output capacitor 1(1) 100 µF
TJ Junction temperature –40 125 °C
(1) Adjustable voltage version only. When using feedback resistors that are smaller than recommended, the minimum output capacitance must be greater than 5 µF.

6.4 Thermal Information

THERMAL METRIC(1) TPS717-Q1 UNIT
DCK (SOT) DRV (WSON) DSE (WSON)
5 PINS 6 PINS 6 PINS
RθJA Junction-to-ambient thermal resistance 279.2 71.1 190.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 57.5 96.5 94.9 °C/W
RθJB Junction-to-board thermal resistance 74.1 40.5 149.3 °C/W
ψJT Junction-to-top characterization parameter 0.8 2.7 6.4 °C/W
ψJB Junction-to-board characterization parameter 73.1 40.9 152.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a 10.7 n/a °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

Over operating temperature range (TJ, TA = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.5 V, whichever is greater; IOUT = 0.5 mA, VEN = VIN, COUT = 1 μF, CNR = 0.01 μF, unless otherwise noted. For the adjustable version (TPS71701-Q1), VOUT = 2.8 V. Typical values are at TA = 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range(1) 2.5 6.5 V
VFB Feedback pin voltage (TPS71701) IOUT = 5 mA –2% 0.793 2% V
VOUT Output voltage range TPS717-Q1 0.9 5 V
TPS71701-Q1 0.9 6.5 – VDO
VOUT Output accuracy (nominal) TA = 25°C ±2.5 mV
Output accuracy
(VOUT < 1 V)		 Over VIN, IOUT, temperature(3) VOUT + 0.5 V ≤ VIN ≤ 6.5 V,
0 mA ≤ IOUT ≤ 150 mA		 –30 30
Output accuracy
(VOUT ≥ 1 V)		 Over VIN, IOUT, temperature(3) VOUT + 0.5 V ≤ VIN ≤ 6.5 V,
0 mA ≤ IOUT ≤ 150 mA		 –3% 3%
ΔVOUT(ΔVIN) Line regulation(1) VOUT(nom) + 0.5 V ≤ VIN ≤ 6.5 V,
IOUT = 5 mA		 125 μV/V
ΔVOUT(ΔIOUT) Load regulation 0 mA ≤ IOUT ≤ 150 mA 70 μV/mA
VDO Dropout voltage(2)
(VIN = VOUT(nom) – 0.1 V)		 IOUT = 150 mA 170 300 mV
ILIM (fixed) Output current limit (fixed output) VOUT = 0.9 × VOUT(nom) 200 325 575 mA
ILIM (adjustable) Output current limit (TPS71701-Q1) VOUT = 0.9 × VOUT(nom) 200 325 575 mA
IGND Ground pin current IOUT = 0.1 mA 45 80 μA
IOUT = 150 mA 100
ISHDN Shutdown current (IGND) VEN ≤ 0.4 V, 2.5 V ≤ VIN < 4.5 V,
TA = –40°C to 125°C		 0.20 1.5 μA
VEN ≤ 0.4 V, 4.5 V ≤ VIN ≤ 6.5 V,
TA = –40°C to 125°C		 0.90
VEN ≤ 0.4 V, 2.5 V ≤ VIN < 4.5 V,
TA = –40°C to 125°C, DRV package		 2
IFB Feedback pin current (TPS71701-Q1) 0.02 1 μA
PSRR Power-supply rejection ratio VIN = 3.8 V,
VOUT = 2.8 V,
IOUT = 150 mA		 f = 100 Hz 70 dB
f = 1 kHz 70
f = 10 kHz 67
f = 100 kHz 67
f = 1 MHz 45
Vn Output noise voltage BW = 100 Hz to 100 kHz,
VIN = 3.8 V,
VOUT = 2.8 V,
IOUT = 10 mA		 CNR = none 95 × VOUT μVRMS/V
CNR = 0.001 μF 25 × VOUT
CNR = 0.01 μF 12.5 × VOUT
CNR = 0.1 μF 11.5 × VOUT
tSTR Startup time VOUT = 90% VOUT(nom),
RL = 19 Ω,
COUT = 1 μF		 0.9 V ≤ VOUT ≤ 1.6 V, CNR = 0.001 μF 0.700 ms
1.6 V < VOUT < VOUT(max), CNR = 0.01 μF 0.160
VEN(high) Enable high (enabled) VIN ≤ 5.5 V 1.2 6.5(4) V
5.5 V < VIN ≤ 6.5 V 1.25 6.5
VEN(low) Enable low (shutdown) 0 0.4 V
IEN(high) Enable pin current, enabled EN = 6.5 V 0.02 1 μA
Tsd Thermal shutdown temperature Shutdown, temperature increasing 160 °C
Reset, temperature decreasing 140
UVLO Undervoltage lockout VIN rising 2.45 2.49 V
Hysteresis VIN falling 150 mV
(1) Minimum VIN = VOUT + VDO or 2.5 V, whichever is greater.
(2) VDO is not measured for devices with VOUT(nom) < 2.6 V because minimum VIN = 2.5 V.
(3) Does not include external resistor tolerances.
(4) Maximum VEN(high) = VIN + 0.3 or 6.5 V, whichever is smaller.

6.6 Typical Characteristics

Over operating temperature range (TJ, TA = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.5 V, whichever is greater; IOUT = 0.5 mA, VEN = VIN, COUT = 1 μF, CNR = 0.01 μF, unless otherwise noted. For the adjustable version (TPS71701-Q1), VOUT = 2.8 V. Typical values are at TA = 25°C.
TPS717-Q1 tc_load_bvs068.gif
Figure 1. Load Regulation
TPS717-Q1 tc_line_bvs068.gif
Figure 3. Line Regulation (IOUT = 5 mA)
TPS717-Q1 tc_vout_temp_bvs068.gif
Figure 5. Output Voltage vs Temperature
TPS717-Q1 tc_vdo_temp_bvs068.gif
Figure 7. Dropout Voltage vs Temperature
TPS717-Q1 tc_ignd_io_bvs068.gif
Figure 9. Ground Pin Current vs Output Current
TPS717-Q1 tc_ignd_temp_dis_bvs068.gif
Figure 11. Ground Pin Current vs Temperature (Disabled)
TPS717-Q1 tc_psrr_fqcy01_bvs068.gif
Figure 13. Power-Supply Ripple Rejection vs Frequency (VIN – VOUT = 1 V)
TPS717-Q1 tc_psrr_fqcy03_bvs068.gif
Figure 15. Power-Supply Ripple Rejection vs Frequency in Dropout Conditions (VIN – VOUT = 0.25 V)
TPS717-Q1 tc_psrr_fqcy05_bvs068.gif
Figure 17. Power-Supply Ripple Rejection vs Frequency in Dropout Conditions (VIN – VOUT = 0.25 V)
TPS717-Q1 tc_psrr_iout01_bvs068.gif
Figure 19. Power-Supply Ripple Rejection vs (VIN – VOUT)
TPS717-Q1 tc_psrr_iout03_bvs068.gif
Figure 21. Power-Supply Ripple Rejection vs (VIN – VOUT)
TPS717-Q1 tc_noise_cout_bvs068.gif
Figure 23. Output Spectral Noise Density vs
Output Capacitance
TPS717-Q1 tc_noisetotal_cnr_bvs068.gif
Figure 25. Total Output Noise vs Noise Reduction
TPS717-Q1 tc_line_tr_slvsbm4.gif
Figure 27. Line Transient Response
TPS717-Q1 tc_turn-on_bvs068.gif
Figure 29. Turn-On Response
TPS717-Q1 tc_light_load_bvs068.gif
Figure 2. Load Regulation Under Light Loads
TPS717-Q1 tc_line02_bvs068.gif
Figure 4. Line Regulation (IOUT = 150 mA)
TPS717-Q1 tc_vdo_io_bvs068.gif
Figure 6. Dropout Voltage vs Output Current
TPS717-Q1 tc_ignd_vin_bvs068.gif
Figure 8. Ground Pin Current vs Input Voltage
TPS717-Q1 tc_ignd_temp_en_bvs068.gif
Figure 10. Ground Pin Current vs Temperature (Enabled)
TPS717-Q1 tc_iclamp_vin_bvs068.gif
Figure 12. Current Limit vs Input Voltage
TPS717-Q1 tc_psrr_fqcy02_bvs068.gif
Figure 14. Power-Supply Ripple Rejection vs Frequency (VIN – VOUT = 0.5 V)
TPS717-Q1 tc_psrr_fqcy04_bvs068.gif
Figure 16. Power-Supply Ripple Rejection vs Frequency (VIN – VOUT = 1 V)
TPS717-Q1 tc_psrr_fqcy06_bvs068.gif
Figure 18. Power-Supply Ripple Rejection vs Frequency (VIN – VOUT = 1 V)
TPS717-Q1 tc_psrr_iout02_bvs068.gif
Figure 20. Power-Supply Ripple Rejection vs (VIN – VOUT)
TPS717-Q1 tc_noise_iout_bvs068.gif
Figure 22. Output Spectral Noise Density vs
Output Current
TPS717-Q1 tc_noise_cnr_bvs068.gif
Figure 24. Output Spectral Noise Density vs
Noise Reduction
TPS717-Q1 tc_noisetotal_cout_bvs068.gif
Figure 26. Total Output Noise vs Output Capacitance
TPS717-Q1 tc_load_tr_slvsbm4.gif
Figure 28. Load Transient Response
TPS717-Q1 tc_pupd_bvs068.gif
Figure 30. Power-Up and Power-Down