JAJS390D March   2001  – February 2018 TPS791

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図: 固定出力
      2.      概略回路図: 可変出力
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Power Dissipation and Junction Temperature
      2. 7.3.2 Programming the TPS79101 Adjustable Regulator
      3. 7.3.3 Regulator Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 External Capacitor Requirements
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout Recommendation to Improve PSRR and Noise Performance
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DBV|5
  • DBV|6
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

DBV Package: Adjustable Output
6-Pin SOT23
Top View
DBV Package: Fixed Output
5-Pin SOT23
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME ADJ FIXED
BYPASS 4 4 — An external bypass capacitor connected to this pin, in conjunction with an internal resistor, creates a low-pass filter to further reduce regulator noise.
EN 3 3 I The EN pin is an input which enables or shuts down the device. The enable signal is an active-low digital control that enables the device, so when EN is a logic high (> 2 V), the device is in shutdown mode. When EN is logic low (< 0.7 V), the device is enabled.
FB 5 N/A I This pin is the feedback input voltage for the adjustable device.
GND 2 2 — Regulator ground.
IN 1 1 I The IN pin is the input to the device.
OUT 6 5 O The OUT pin is the regulated output of the device.