JAJSCI9A May   2016  – September 2016 TPS7A19

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable Pin (EN)
      2. 7.3.2 Regulated Output Pin (OUT)
      3. 7.3.3 Power-Good Pin (PG)
      4. 7.3.4 Delay Timer Pin (DELAY)
      5. 7.3.5 Adjustable Output Voltage (ADJ for TPS7A1901)
      6. 7.3.6 Undervoltage Shutdown
      7. 7.3.7 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation With VIN < 4 V
      2. 7.4.2 Operation With EN Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Power Dissipation and Thermal Considerations
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
        1. 11.1.1.1 評価モジュール
        2. 11.1.1.2 SPICEモデル
      2. 11.1.2 デバイスの項目表記
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

DRB Package
8-Pin SON With Thermal Pad
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
DELAY 1 — Delay pin. Connect a capacitor to GND to adjust the PG delay time; leave open if the PG function is not needed.
EN 6 I Enable pin. This pin turns the regulator on or off. If VEN ≥ VEN_HI, the regulator is enabled. If VEN ≤ VEN_LO, the regulator is disabled. If not used, the EN pin can be connected to IN.
FB 3 I Feedback pin. The feedback pin is the input to the control-loop error amplifier.
GND 4,5 — Ground pin.
IN 7 I Regulator input supply pin.
OUT 2 O Regulator output pin. When the output voltage is larger than 2.5 V, connect a 10-μF to 500-μF ceramic capacitor with an equivalent series resistance (ESR) from 0.001 to 20 Ω to assure stability. When the output voltage is from 1.5 V to 2.5 V, the minimum, stable capacitor value should be 22 μF.
PG 8 O Power good. This open-drain pin must be connected to VOUT through an external resistor. PG is pulled low when the output voltage goes below threshold.
Thermal pad — Solder to printed-circuit-board (PCB) to enhance thermal performance. Although the thermal pad can be left floating, connect the thermal pad to the ground plane for optimal performance.