Noise can be generally defined as any unwanted signal combining with the desired signal (such as the regulated LDO output). Noise can easily be noticed in audio as a hissing or popping sound. Noise produced from an external circuit or the 50- to 60-hertz power-line noise (spikes), along with the harmonics, is an excellent representative of extrinsic noise. Intrinsic noise is produced by components within the device circuitry, such as resistors and transistors. The two dominating sources of intrinsic noise are the error amplifier and the internal reference voltage (V_NR/SS). Extrinsic noise, including the switching mode power-supply ac ripple voltage, coupled onto the input supply of the LDO is attenuated by the LDO power-supply rejection ratio, or PSRR. PSRR is a measurement of the noise attenuation from the input to the output of the LDO.

Optimize the intrinsic noise and PSRR by carefully selecting:

• C_NR/SS for the low-frequency range up to the device bandwidth
• C_OUT for the high-frequency range close to and higher than the device bandwidth
• Operating headroom, V_IN – V_OUT (V_DO), mainly for the low-frequency range up to the device bandwidth, but also for higher frequencies to a lesser effect

These behaviors are described in the Typical Characteristics curves.

Figure 8-14 shows the measured PSRR for a 1.2-V device output voltage with a 0.7-V headroom for 1-A, 1.5-A, and 2-A load currents. Table 8-3 lists the typical output noise for these capacitors.

Figure 8-14 PSRR vs Frequency and I_OUT for V_OUT = 1.2 V, C_OUT = 10 μF

PSRR can be viewed as being simply the ratio of the output capacitor impedance by the LDO output impedance. At low frequency, the output impedance is very low whereas the output impedance of the capacitor is high, resulting in high PSRR. As the frequency increases, the output capacitor impedance reduces and reaches a minima set by the ESR.

As given in Figure 8-14, to achieve high PSRR at high frequencies, make sure that the output capacitor equivalent series resistance (ESR) and equivalent series inductance (ESL) are minimal. This figure shows how to use a single 10-μF output capacitor implementation. However, minimizing the ESR- and ESL-generated resonance point in the output capacitance allows for a smoother transition between the LDO active PSRR component to the passive PSRR of the capacitors, therefore using output capacitors in parallel helps above 200 kHz, improving the PSRR by 5 dB to 7 dB.