JAJSM29A april   2023  – july 2023 TPS7A96

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Voltage Setting and Regulation
      2. 7.3.2 Ultra-Low Noise and Ultra-High Power-Supply Rejection Ratio (PSRR)
      3. 7.3.3 Programmable Current Limit and Power-Good Threshold
      4. 7.3.4 Programmable Soft-Start (NR/SS Pin)
      5. 7.3.5 Precision Enable and UVLOs
      6. 7.3.6 Active Discharge
      7. 7.3.7 Thermal Shutdown Protection (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
      4. 7.4.4 Current-Limit Operation
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Output Voltage Restart (Overshoot Prevention Circuit)
      2. 8.1.2  Precision Enable (External UVLO)
      3. 8.1.3  Undervoltage Lockout (UVLO) Operation
      4. 8.1.4  Dropout Voltage (VDO)
      5. 8.1.5  Power-Good Feedback (FB_PG Pin) and Power-Good Threshold (PG Pin)
      6. 8.1.6  Adjusting the Factory-Programmed Current Limit
      7. 8.1.7  Programmable Soft-Start and Noise-Reduction (NR/SS Pin)
      8. 8.1.8  Inrush Current
      9. 8.1.9  Optimizing Noise and PSRR
      10. 8.1.10 Adjustable Operation
      11. 8.1.11 Paralleling for Higher Output Current and Lower Noise
      12. 8.1.12 Recommended Capacitor Types
      13. 8.1.13 Load Transient Response
      14. 8.1.14 Power Dissipation (PD)
      15. 8.1.15 Estimating Junction Temperature
      16. 8.1.16 TPS7A96EVM-106 Thermal Analysis
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 Evaluation Modules
        2. 9.1.1.2 Spice Models
      2. 9.1.2 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.1.11 Paralleling for Higher Output Current and Lower Noise

Achieving higher output current and lower noise is achievable by paralleling two or more LDOs. Implementation must be carefully planned out to optimize performance and minimize output current imbalance.

Because the TPS7A96 output voltage is set by a resistor driven by a current source, the NR/SS resistor and capacitor must be adjusted as per the following:

Equation 8. R N R / S S _ P a r a l l e l = V O U T _ T A R G E T n  ×  I N R / S S
Equation 9. C N R / S S _ P a r a l l e l = n  ×  C N R / S S _ S i n g l e

where:

  • n is the number of LDOs in parallel
  • INR/SS is the NR/SS current as provided in the data sheet Electrical Characteristics table
  • CNR/SS_single is the NR/SS capacitor for a single LDO

When connecting the input and NR/SS pin together, and with the LDO being a buffer, the current imbalance is only affected by the error offset voltage of the error amplifier. As such, the current imbalance can be expressed as:

Equation 10. ε I = V O S   ×   2   ×   R B A L L A S T R B A L L A S T 2  -  ∆ R B A L L A S T 2

where:

  • εI is the current imbalance
  • VOS is the LDO error offset voltage
  • RBALLAST is the ballast resistor
  • ΔRBALLAST is the deviation of the ballast resistor value from the nominal value

With the typical offset voltage of 200 μV, considering no error from the design of the PCB ballast resistor (ΔRBALLAST = 0) and a 100-mA maximum current imbalance, the ballast resistor must be 4 mΩ or greater; see Figure 8-16.

Using the configuration described, the LDO output noise is reduced by:

Equation 11. e O _ p a r a l l e l  =  1 n   ×   e O _ s i n g l e

where:

  • n is the numbers of LDOs in parallel
  • eO_single is the output noise density from a single LDO
  • eO_parallel is the output noise density for the resulting parallel LDO

In Figure 8-16, the noise is reduced by 1 / √2.

GUID-20230323-SS0I-Q6TQ-RMZP-DL6BV3HZ62RF-low.gif Figure 8-16 Paralleling Multiple TPS7A96 Devices