JAJSLN2 November   2021 TPS7H1210-SEP

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Internal Current Limit
      2. 7.3.2 Enable Pin Operation
      3. 7.3.3 Programmable Soft-Start
      4. 7.3.4 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Adjustable Operation
      2. 8.1.2 Capacitor Recommendations
      3. 8.1.3 Noise Reduction and Feed-Forward Capacitor Requirements
      4. 8.1.4 Power-Supply Rejection Ratio (PSRR)
      5. 8.1.5 Output Noise
      6. 8.1.6 Transient Response
      7. 8.1.7 Post DC-DC Converter Filtering
      8. 8.1.8 Power for Precision Analog
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don’ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Improve PSRR and Noise Performance
    2. 10.2 Layout Example
    3. 10.3 Thermal Performance
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Spice Models
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.2 Detailed Design Procedure

The design consists of CIN, COUT, CNR_SS, RFB_TOP, RFB_BOT, REN_TOP, REN_BOT, and the circuit shown in GUID-C89E1021-DD2D-4B4A-AEAE-1B800333FB58.html#SBVS1691608.

The first step when designing with a linear regulator is to examine the maximum load current along with the input and output voltage requirements to determine if the device thermal and dropout voltage requirements can be met. At 1 A, the input dropout voltage of the TPS7H1210-SEP device is a maximum of 500 mV over temperature; thus, the dropout headroom is sufficient for operation over both input and output voltage accuracy. Keep in mind that operating an LDO close to the dropout limit reduces AC performance, but has the benefit of reducing the power dissipation across the LDO.

The maximum power dissipated in the linear regulator is the maximum voltage drop across the pass element from the input to the output multiplied by the maximum load current (plus a small amount of quiescent power). In this example, the maximum voltage drop across in the pass element is (–6 V) – (–5 V), giving us a VDROP = 1 V. The power dissipated in the pass element is calculated by taking this voltage drop multiplied by the maximum load current. For this example, the maximum power dissipated in the linear regulator is approximately 1 W.

To ensure an accurate output voltage, RFB_TOP and RFB_BOT must also be found, and the current through these resistors must be greater than 5 µA to ensure stability. For this design, RFB_TOP is set to 34 kΩ, to achieve reasonable leakage current leakage while continuing to hold it well above 5 µA. Then #SBVS1692188 is used to calculate the proper value for RFB_BOT.

Equation 3. R F B _ B O T = R F B _ T O P × V R E F V O U T - V R E F = 10.5   k Ω   a n d   I D I V I D E R = V R E F R F B _ B O T = 112.6   µ A

Next, for CIN a 10 µF, 1 µF, and 0.1-µF ceramic capacitor are selected. This provides margin over the 10-µF minimum input capacitance and reduces the impedance across a wider range of frequencies than a single 10-µF capacitor.

For COUT, 5 × 10-µF, 1 × 100-nF, and 1 × 10-nF ceramic capacitors are selected. The multiple ceramic capacitors reduce ESR (equivalent series resistance) and ESL (equivalent series inductance) to aid in good AC performance. Additionally, better SET (single-event-transient) performance is generally achieved by choosing a larger output capacitance than the minimum of 10 µF.

Next, CNR_SS is set at 100 nF for optimal noise performance along with maximized AC performance while keeping reasonable soft-start times.

To have a configurable turn-on voltage, feed the EN pin by a resistor divider from VIN to GND. Since the TPS7H1210-SEP is commanded to turn-on when EN is less than –2 V (see VEN(-HI) in GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000240550.html#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000240550), #EQUATION-BLOCK_AT2_QTK_NRB can be used to determine the resistors to select for a desired turn-on voltage, VIN(turn-on).

Equation 4. R E N _ B O T = R E N _ T O P × 2   V V I N ( t u r n - o n ) - 2   V

For this design REN_TOP = 102 kΩ and REN_BOT = 68 kΩ, which results in VIN(turn-on) = –5 V. This means that as VIN is ramping from 0 V to its final value of –6 V during start-up, the regulator will turn-on when VIN reaches –5 V.