JAJSJM2B July   2022  – April 2024 TPS929240-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Device Bias and Power
        1. 6.3.1.1 Power Bias (VBAT)
        2. 6.3.1.2 5V Low-Drop-Out Linear Regulator (VLDO)
        3. 6.3.1.3 Undervoltage Lockout (UVLO) and Power-On-Reset (POR)
        4. 6.3.1.4 Power Supply (SUPPLY)
        5. 6.3.1.5 Programmable Low Supply Warning
      2. 6.3.2 Constant Current Output
        1. 6.3.2.1 Reference Current with External Resistor (REF)
        2. 6.3.2.2 64-Step Programmable High-Side Constant-Current Output
      3. 6.3.3 PWM Dimming
        1. 6.3.3.1 PWM Generator
        2. 6.3.3.2 PWM Dimming Frequency
        3. 6.3.3.3 Blank Time
        4. 6.3.3.4 Phase Shift PWM Dimming
        5. 6.3.3.5 Linear Brightness Control
        6. 6.3.3.6 Exponential Brightness Control
      4. 6.3.4 FAIL-SAFE State Operation
      5. 6.3.5 On-Chip, 8-Bit, Analog-to-Digital Converter (ADC)
        1. 6.3.5.1 Minimum On Time for ADC Measurement
        2. 6.3.5.2 ADC Auto Scan
        3. 6.3.5.3 ADC Error
      6. 6.3.6 Diagnostic and Protection in NORMAL State
        1. 6.3.6.1  VBAT Undervoltage Lockout Diagnostics in NORMAL state
        2. 6.3.6.2  Low-Supply Warning Diagnostics in NORMAL State
        3. 6.3.6.3  Supply Undervoltage Diagnostics in NORMAL State
        4. 6.3.6.4  Reference Diagnostics in NORMAL state
        5. 6.3.6.5  Pre-Thermal Warning in NORMAL state
        6. 6.3.6.6  Overtemperature Protection in NORMAL state
        7. 6.3.6.7  Overtemperature Shutdown in NORMAL state
        8. 6.3.6.8  LED Open-Circuit Diagnostics in NORMAL state
        9. 6.3.6.9  LED Short-Circuit Diagnostics in NORMAL state
        10. 6.3.6.10 Single-LED Short-Circuit Detection in NORMAL state
        11. 6.3.6.11 EEPROM CRC Error in NORMAL state
        12. 6.3.6.12 Communication Loss Diagnostic in NORMAL State
        13. 6.3.6.13 Fault Masking in NORMAL state
        14.       53
      7. 6.3.7 Diagnostic and Protection in FAIL-SAFE states
        1. 6.3.7.1  Supply Undervoltage Lockout Diagnostics in FAIL-SAFE states
        2. 6.3.7.2  Low-Supply Warning Diagnostics in FAIL-SAFE states
        3. 6.3.7.3  Supply Undervoltage Diagnostics in FAIL-SAFE State
        4. 6.3.7.4  Reference Diagnostics in FAIL-SAFE states
        5. 6.3.7.5  Pre-Thermal Warning in FAIL-SAFE state
        6. 6.3.7.6  Overtemperature Protection in FAIL-SAFE state
        7. 6.3.7.7  Overtemperature Shutdown in FAIL-SAFE state
        8. 6.3.7.8  LED Open-Circuit Diagnostics in FAIL-SAFE state
        9. 6.3.7.9  LED Short-Circuit Diagnostics in FAIL-SAFE state
        10. 6.3.7.10 Single-LED Short-Circuit Detection in FAIL-SAFE state
        11. 6.3.7.11 EEPROM CRC Error in FAIL-SAFE State
        12. 6.3.7.12 Fault Masking in FAIL-SAFE state
        13.       Diagnostics Table in FAIL-SAFE State
      8. 6.3.8 OFAF Setup In FAIL-SAFE state
      9. 6.3.9 ERR Output
    4. 6.4 Device Functional Modes
      1. 6.4.1 POR State
      2. 6.4.2 INITIALIZATION state
      3. 6.4.3 NORMAL state
      4. 6.4.4 FAIL-SAFE state
      5. 6.4.5 PROGRAM state
    5. 6.5 Programming
      1. 6.5.1 FlexWire Protocol
        1. 6.5.1.1 Protocol Overview
        2. 6.5.1.2 UART Interface Address Setting
        3. 6.5.1.3 Status Response
        4. 6.5.1.4 Synchronization Byte
        5. 6.5.1.5 Device Address Byte
        6. 6.5.1.6 Register Address Byte
        7. 6.5.1.7 Data Frame
        8. 6.5.1.8 CRC Frame
        9. 6.5.1.9 Burst Mode
      2. 6.5.2 Registers Lock
      3. 6.5.3 Register Default Data
      4. 6.5.4 EEPROM Programming
        1. 6.5.4.1 Chip Selection by Pulling REF Pin High
        2. 6.5.4.2 Chip Selection by ADDR Pins Configuration
        3. 6.5.4.3 EEPROM Register Access and Burn
        4. 6.5.4.4 EEPROM PROGRAM State Exit
    6. 6.6 Register Maps
      1. 6.6.1 BRT Registers
      2. 6.6.2 IOUT Registers
      3. 6.6.3 CONF Registers
      4. 6.6.4 CTRL Registers
      5. 6.6.5 FLAG Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Smart Rear Lamp with Distributed LED Drivers
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
      4. 7.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

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発注情報

6.6.2 IOUT Registers

Table 6-74 lists the memory-mapped registers for the IOUT registers. All register offset addresses not listed in Table 6-74 should be considered as reserved locations and the register contents should not be modified.

Output Current Setting

Table 6-74 IOUT Registers
OffsetAcronymRegister NameSection
50hIOUTA0Output Current Setting for OUTA0Go
51hIOUTA1Output Current Setting for OUTA1Go
52hIOUTA2Output Current Setting for OUTA2Go
53hIOUTB0Output Current Setting for OUTB0Go
54hIOUTB1Output Current Setting for OUTB1Go
55hIOUTB2Output Current Setting for OUTB2Go
56hIOUTC0Output Current Setting for OUTC0Go
57hIOUTC1Output Current Setting for OUTC1Go
58hIOUTC2Output Current Setting for OUTC2Go
59hIOUTD0Output Current Setting for OUTD0Go
5AhIOUTD1Output Current Setting for OUTD1Go
5BhIOUTD2Output Current Setting for OUTD2Go
5ChIOUTE0Output Current Setting for OUTE0Go
5DhIOUTE1Output Current Setting for OUTE1Go
5EhIOUTE2Output Current Setting for OUTE2Go
5FhIOUTF0Output Current Setting for OUTF0Go
60hIOUTF1Output Current Setting for OUTF1Go
61hIOUTF2Output Current Setting for OUTF2Go
62hIOUTG0Output Current Setting for OUTG0Go
63hIOUTG1Output Current Setting for OUTG1Go
64hIOUTG2Output Current Setting for OUTG2Go
65hIOUTH0Output Current Setting for OUTH0Go
66hIOUTH1Output Current Setting for OUTH1Go
67hIOUTH2Output Current Setting for OUTH2Go

Complex bit access types are encoded to fit into small table cells. Table 6-75 shows the codes that are used for access types in this section.

Table 6-75 IOUT Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

6.6.2.1 IOUTA0 Register (Offset = 50h) [Reset = X]

IOUTA0 is shown in Figure 6-72 and described in Table 6-76.

Return to the Summary Table.

Figure 6-72 IOUTA0 Register
76543210
RESERVEDIOUTA0
R-0hR/W-X
Table 6-76 IOUTA0 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0h Reserved
5-0IOUTA0R/WX Output current setting for OUTA0
Load EEPROM register data when reset

6.6.2.2 IOUTA1 Register (Offset = 51h) [Reset = X]

IOUTA1 is shown in Figure 6-73 and described in Table 6-77.

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Figure 6-73 IOUTA1 Register
76543210
RESERVEDIOUTA1
R-0hR/W-X
Table 6-77 IOUTA1 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0h Reserved
5-0IOUTA1R/WX Output current setting for OUTA1
Load EEPROM register data when reset

6.6.2.3 IOUTA2 Register (Offset = 52h) [Reset = X]

IOUTA2 is shown in Figure 6-74 and described in Table 6-78.

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Figure 6-74 IOUTA2 Register
76543210
RESERVEDIOUTA2
R-0hR/W-X
Table 6-78 IOUTA2 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0h Reserved
5-0IOUTA2R/WX Output current setting for OUTA2
Load EEPROM register data when reset

6.6.2.4 IOUTB0 Register (Offset = 53h) [Reset = X]

IOUTB0 is shown in Figure 6-75 and described in Table 6-79.

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Figure 6-75 IOUTB0 Register
76543210
RESERVEDIOUTB0
R-0hR/W-X
Table 6-79 IOUTB0 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0h Reserved
5-0IOUTB0R/WX Output current setting for OUTB0
Load EEPROM register data when reset

6.6.2.5 IOUTB1 Register (Offset = 54h) [Reset = X]

IOUTB1 is shown in Figure 6-76 and described in Table 6-80.

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Figure 6-76 IOUTB1 Register
76543210
RESERVEDIOUTB1
R-0hR/W-X
Table 6-80 IOUTB1 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0h Reserved
5-0IOUTB1R/WX Output current setting for OUTB1
Load EEPROM register data when reset

6.6.2.6 IOUTB2 Register (Offset = 55h) [Reset = X]

IOUTB2 is shown in Figure 6-77 and described in Table 6-81.

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Figure 6-77 IOUTB2 Register
76543210
RESERVEDIOUTB2
R-0hR/W-X
Table 6-81 IOUTB2 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0h Reserved
5-0IOUTB2R/WX Output current setting for OUTB2
Load EEPROM register data when reset

6.6.2.7 IOUTC0 Register (Offset = 56h) [Reset = X]

IOUTC0 is shown in Figure 6-78 and described in Table 6-82.

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Figure 6-78 IOUTC0 Register
76543210
RESERVEDIOUTC0
R-0hR/W-X
Table 6-82 IOUTC0 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0h Reserved
5-0IOUTC0R/WX Output current setting for OUTC0
Load EEPROM register data when reset

6.6.2.8 IOUTC1 Register (Offset = 57h) [Reset = X]

IOUTC1 is shown in Figure 6-79 and described in Table 6-83.

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Figure 6-79 IOUTC1 Register
76543210
RESERVEDIOUTC1
R-0hR/W-X
Table 6-83 IOUTC1 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0h Reserved
5-0IOUTC1R/WX Output current setting for OUTC1
Load EEPROM register data when reset

6.6.2.9 IOUTC2 Register (Offset = 58h) [Reset = X]

IOUTC2 is shown in Figure 6-80 and described in Table 6-84.

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Figure 6-80 IOUTC2 Register
76543210
RESERVEDIOUTC2
R-0hR/W-X
Table 6-84 IOUTC2 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0h Reserved
5-0IOUTC2R/WX Output current setting for OUTC2
Load EEPROM register data when reset

6.6.2.10 IOUTD0 Register (Offset = 59h) [Reset = X]

IOUTD0 is shown in Figure 6-81 and described in Table 6-85.

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Figure 6-81 IOUTD0 Register
76543210
RESERVEDIOUTD0
R-0hR/W-X
Table 6-85 IOUTD0 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0h Reserved
5-0IOUTD0R/WX Output current setting for OUTD0
Load EEPROM register data when reset

6.6.2.11 IOUTD1 Register (Offset = 5Ah) [Reset = X]

IOUTD1 is shown in Figure 6-82 and described in Table 6-86.

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Figure 6-82 IOUTD1 Register
76543210
RESERVEDIOUTD1
R-0hR/W-X
Table 6-86 IOUTD1 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0h Reserved
5-0IOUTD1R/WX Output current setting for OUTD1
Load EEPROM register data when reset

6.6.2.12 IOUTD2 Register (Offset = 5Bh) [Reset = X]

IOUTD2 is shown in Figure 6-83 and described in Table 6-87.

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Figure 6-83 IOUTD2 Register
76543210
RESERVEDIOUTD2
R-0hR/W-X
Table 6-87 IOUTD2 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0h Reserved
5-0IOUTD2R/WX Output current setting for OUTD2
Load EEPROM register data when reset

6.6.2.13 IOUTE0 Register (Offset = 5Ch) [Reset = X]

IOUTE0 is shown in Figure 6-84 and described in Table 6-88.

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Figure 6-84 IOUTE0 Register
76543210
RESERVEDIOUTE0
R-0hR/W-X
Table 6-88 IOUTE0 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0h Reserved
5-0IOUTE0R/WX Output current setting for OUTE0
Load EEPROM register data when reset

6.6.2.14 IOUTE1 Register (Offset = 5Dh) [Reset = X]

IOUTE1 is shown in Figure 6-85 and described in Table 6-89.

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Figure 6-85 IOUTE1 Register
76543210
RESERVEDIOUTE1
R-0hR/W-X
Table 6-89 IOUTE1 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0h Reserved
5-0IOUTE1R/WX Output current setting for OUTE1
Load EEPROM register data when reset

6.6.2.15 IOUTE2 Register (Offset = 5Eh) [Reset = X]

IOUTE2 is shown in Figure 6-86 and described in Table 6-90.

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Figure 6-86 IOUTE2 Register
76543210
RESERVEDIOUTE2
R-0hR/W-X
Table 6-90 IOUTE2 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0h Reserved
5-0IOUTE2R/WX Output current setting for OUTE2
Load EEPROM register data when reset

6.6.2.16 IOUTF0 Register (Offset = 5Fh) [Reset = X]

IOUTF0 is shown in Figure 6-87 and described in Table 6-91.

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Figure 6-87 IOUTF0 Register
76543210
RESERVEDIOUTF0
R-0hR/W-X
Table 6-91 IOUTF0 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0h Reserved
5-0IOUTF0R/WX Output current setting for OUTF0
Load EEPROM register data when reset

6.6.2.17 IOUTF1 Register (Offset = 60h) [Reset = X]

IOUTF1 is shown in Figure 6-88 and described in Table 6-92.

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Figure 6-88 IOUTF1 Register
76543210
RESERVEDIOUTF1
R-0hR/W-X
Table 6-92 IOUTF1 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0h Reserved
5-0IOUTF1R/WX Output current setting for OUTF1
Load EEPROM register data when reset

6.6.2.18 IOUTF2 Register (Offset = 61h) [Reset = X]

IOUTF2 is shown in Figure 6-89 and described in Table 6-93.

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Figure 6-89 IOUTF2 Register
76543210
RESERVEDIOUTF2
R-0hR/W-X
Table 6-93 IOUTF2 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0h Reserved
5-0IOUTF2R/WX Output current setting for OUTF2
Load EEPROM register data when reset

6.6.2.19 IOUTG0 Register (Offset = 62h) [Reset = X]

IOUTG0 is shown in Figure 6-90 and described in Table 6-94.

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Figure 6-90 IOUTG0 Register
76543210
RESERVEDIOUTG0
R-0hR/W-X
Table 6-94 IOUTG0 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0h Reserved
5-0IOUTG0R/WX Output current setting for OUTG0
Load EEPROM register data when reset

6.6.2.20 IOUTG1 Register (Offset = 63h) [Reset = X]

IOUTG1 is shown in Figure 6-91 and described in Table 6-95.

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Figure 6-91 IOUTG1 Register
76543210
RESERVEDIOUTG1
R-0hR/W-X
Table 6-95 IOUTG1 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0h Reserved
5-0IOUTG1R/WX Output current setting for OUTG1
Load EEPROM register data when reset

6.6.2.21 IOUTG2 Register (Offset = 64h) [Reset = X]

IOUTG2 is shown in Figure 6-92 and described in Table 6-96.

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Figure 6-92 IOUTG2 Register
76543210
RESERVEDIOUTG2
R-0hR/W-X
Table 6-96 IOUTG2 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0h Reserved
5-0IOUTG2R/WX Output current setting for OUTG2
Load EEPROM register data when reset

6.6.2.22 IOUTH0 Register (Offset = 65h) [Reset = X]

IOUTH0 is shown in Figure 6-93 and described in Table 6-97.

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Figure 6-93 IOUTH0 Register
76543210
RESERVEDIOUTH0
R-0hR/W-X
Table 6-97 IOUTH0 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0h Reserved
5-0IOUTH0R/WX Output current setting for OUTH0
Load EEPROM register data when reset

6.6.2.23 IOUTH1 Register (Offset = 66h) [Reset = X]

IOUTH1 is shown in Figure 6-94 and described in Table 6-98.

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Figure 6-94 IOUTH1 Register
76543210
RESERVEDIOUTH1
R-0hR/W-X
Table 6-98 IOUTH1 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0h Reserved
5-0IOUTH1R/WX Output current setting for OUTH1
Load EEPROM register data when reset

6.6.2.24 IOUTH2 Register (Offset = 67h) [Reset = X]

IOUTH2 is shown in Figure 6-95 and described in Table 6-99.

Return to the Summary Table.

Figure 6-95 IOUTH2 Register
76543210
RESERVEDIOUTH2
R-0hR/W-X
Table 6-99 IOUTH2 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0h Reserved
5-0IOUTH2R/WX Output current setting for OUTH2
Load EEPROM register data when reset