JAJSFO6F December   2015  – April 2019 TPS99000-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     標準的なスタンドアロン・システム
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions - Initialization, Clock, and Diagnostics
    2.     Pin Functions - Power and Ground
    3.     Pin Functions - Power Supply Management
    4.     Pin Functions - Illumination Control
    5.     Pin Functions - Serial Peripheral Interfaces
    6.     Pin Functions - Analog to Digital Converter
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics - Transimpedance Amplifier Parameters
    6. 7.6  Electrical Characteristics - Digital to Analog Converters
    7. 7.7  Electrical Characteristics - Analog to Digital Converter
    8. 7.8  Electrical Characteristics - FET Gate Drivers
    9. 7.9  Electrical Characteristics - Photo Comparator
    10. 7.10 Electrical Characteristics - Voltage Regulators
    11. 7.11 Electrical Characteristics - Temperature and Voltage Monitors
    12. 7.12 Electrical Characteristics - Current Consumption
    13. 7.13 Power-Up Timing Requirements
    14. 7.14 Power-Down Timing Requirements
    15. 7.15 Timing Requirements - Sequencer Clock
    16. 7.16 Timing Requirements - Host / Diagnostic Port SPI Interface
    17. 7.17 Timing Requirements - ADC Interface
    18. 7.18 Switching Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Illumination Control
        1. 8.3.1.1 Illumination System High Dynamic Range Dimming Overview
        2. 8.3.1.2 Illumination Control Loop
        3. 8.3.1.3 Continuous Mode Operation
          1. 8.3.1.3.1 Output Capacitance in Continuous Mode
          2. 8.3.1.3.2 Continuous Mode Driver Distortion and Blanking Current
          3. 8.3.1.3.3 Continuous Mode S_EN2 Dissipative Load Shunt Options
          4. 8.3.1.3.4 Continuous Mode Constant OFF Time
          5. 8.3.1.3.5 Continuous Mode Current Limit
        4. 8.3.1.4 Discontinuous Mode Operation
          1. 8.3.1.4.1 Discontinuous Mode Pulse Width Limit
          2. 8.3.1.4.2 COMPOUT_LOW Timer in Discontinuous Operation
          3. 8.3.1.4.3 Dimming Within Discontinuous Operation Range
          4. 8.3.1.4.4 Multiple Pulse Heights to Increase Bit Depth
          5. 8.3.1.4.5 TIA Gain Adjustment
          6. 8.3.1.4.6 Current Limit in Discontinuous Mode
          7. 8.3.1.4.7 CMODE Big Cap Mode in Discontinuous Operation
      2. 8.3.2 Over-Brightness Detection
        1. 8.3.2.1 Photo Feedback Monitor BIST
        2. 8.3.2.2 Excessive Brightness BIST
      3. 8.3.3 Analog to Digital Converter
        1. 8.3.3.1 Analog to Digital Converter Input Table
      4. 8.3.4 Power Sequencing and Monitoring
        1. 8.3.4.1 Power Monitoring
      5. 8.3.5 DMD Mirror Voltage Regulator
      6. 8.3.6 Low Dropout Regulators
      7. 8.3.7 System Monitoring Features
        1. 8.3.7.1 Windowed Watchdog Circuits
        2. 8.3.7.2 Die Temperature Monitors
        3. 8.3.7.3 External Clock Ratio Monitor
      8. 8.3.8 Communication Ports
        1. 8.3.8.1 Serial Peripheral Interface (SPI)
    4. 8.4 Device Functional Modes
      1. 8.4.1 OFF
      2. 8.4.2 STANDBY
      3. 8.4.3 POWERING_DMD
      4. 8.4.4 DISPLAY_RDY
      5. 8.4.5 DISPLAY_ON
      6. 8.4.6 PARKING
      7. 8.4.7 SHUTDOWN
    5. 8.5 Register Maps
      1. 8.5.1 System Status Registers
      2. 8.5.2 ADC Control
      3. 8.5.3 General Fault Status
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 HUD
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Application Design Considerations
          1. 9.2.1.2.1 Photodiode Considerations
          2. 9.2.1.2.2 LED Current Measurement
          3. 9.2.1.2.3 Setting the Current Limit
          4. 9.2.1.2.4 Input Voltage Variation Impact
          5. 9.2.1.2.5 Discontinuous Mode Photo Feedback Considerations
          6. 9.2.1.2.6 Transimpedance Amplifiers (TIAs, Usage, Offset, Dark Current, Ranges, RGB Trim)
      2. 9.2.2 Headlight
        1. 9.2.2.1 Design Requirements
  10. 10Power Supply Recommendations
    1. 10.1 TPS99000-Q1 Power Supply Architecture
    2. 10.2 TPS99000-Q1 Power Outputs
    3. 10.3 Power Supply Architecture
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Power/High Current Signals
      2. 11.1.2 Sensitive Analog Signals
      3. 11.1.3 High Speed Digital Signals
      4. 11.1.4 High Power Current Loops
      5. 11.1.5 Kelvin Sensing Connections
      6. 11.1.6 Ground Separation
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 商標
    3. 12.3 静電気放電に関する注意事項
    4. 12.4 Glossary
  13. 13メカニカル、パッケージ、および注文情報
    1. 13.1 Package Option Addendum
      1. 13.1.1 Tape and Reel Information
      2. 13.1.2 Mechanical Drawings

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.1.2.5 Discontinuous Mode Photo Feedback Considerations

System designs should consider the amount of additional capacitance placed in parallel with the photodiode, and the capacitance of the photodiode itself. While the TPS99000-Q1 is designed to function with a very wide range of total capacitance, the lowest light level brightness performance is directly impacted by this capacitance. Higher TIA1 input capacitance will result in a brighter minimum brightness achievable by the system due to this light pulse overrun phenomenon. This results in a reduction of dimming range. (For highest performance, system designer should minimize total capacitance of the photodiode, photodiode cable and connector system).

The leading edge of the light pulse in discontinuous mode is controlled by the charging rate of the capacitance in parallel with the LED. The photo feedback DAC sets the threshold to turn on the shunt FET which shunts the current away from the LED. Latency in the photo feedback loop will result in the light climbing higher than the threshold as shown in Figure 45. The amount of light that occurs after the threshold is reached (shown as hashed green area) is the majority of the light at the lowest discontinuous mode brightness levels. Figure 45 also shows that a reduction in photo feedback DAC level by a factor of two does not reduce the total light pulse power by a factor of two because of the light that occurs after the threshold. The amount of light overrun after the threshold is a function of the photo feedback latency, inductor initial current, capacitance in parallel with the LED, LED voltage to current characteristics and shunt FET timing.

TPS99000-Q1 discontinuous_pulse_overrun_DLPS039.gifFigure 45. Discontinuous Pulse Overrun