SLVSHL7A September   2025  – December 2025 TPSI2240-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Avalanche Robustness
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Dielectric Withstand Testing (HiPot)
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure - Chassis Ground Reference
      4. 9.2.4 Application Performance Plot
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

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発注情報

9.4.2 Layout Example

Varying PCB implementations are possible depending on both the system EMI requirements and the system dielectric withstand testing (HiPot) parameters. The following section detail a TPSI2240-Q1 Circuit Layout Example optimized for best EMI and ESD performance by implementing split resistance architecture on the secondary side.

TPSI2240-Q1 Circuit Layout Example

An example 2-layer circuit layout using the TPSI2240-Q1 is shown below.

TPSI2240-Q1 TPSI2240-Q1 Example Layout - Top LayerFigure 9-13 TPSI2240-Q1 Example Layout - Top Layer
TPSI2240-Q1 TPSI2240-Q1 Example Layout - Bottom LayerFigure 9-14 TPSI2240-Q1 Example Layout - Bottom Layer