JAJSKF5B September   2021  – November 2022 TPSM82864A , TPSM82866A

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Options
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Save Mode
      2. 8.3.2 Forced PWM Mode
      3. 8.3.3 Optimized Transient Performance from PWM to PSM Operation
      4. 8.3.4 Low Dropout Operation (100% Duty Cycle)
      5. 8.3.5 Soft Start
      6. 8.3.6 Switch Current Limit and HICCUP Short-Circuit Protection
      7. 8.3.7 Undervoltage Lockout
      8. 8.3.8 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Enable and Disable (EN)
      2. 8.4.2 Output Discharge
      3. 8.4.3 Power Good (PG)
      4. 8.4.4 Output Voltage and Mode Selection (VSET/MODE)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Setting The Output Voltage
        2. 9.2.2.2 Input and Output Capacitor Selection
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
        1. 9.4.2.1 Thermal Considerations
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.4.3 Power Good (PG)

The device has an open-drain power-good pin, which is specified to sink up to 2 mA. The power-good output requires a pullup resistor connected to any voltage rail less than 5.5 V. The PG signal can be used for sequencing of multiple rails by connecting it to the EN pin of other converters. Leave the PG pin unconnected when not used. Table 8-1 shows the typical PG pin logic.

Table 8-1 PG Pin Logic
DEVICE CONDITIONSLOGIC STATUS
HIGH IMPEDANCELOW
Enable0.9 × VOUT_NOM ≤ VVOUT ≤ 1.1 × VOUT_NOM√
VVOUT < 0.9 × VOUT_NOM or VVOUT > 1.1 × VOUT_NOM√
ShutdownEN = low√
Thermal shutdownTJ > TJSD√
UVLO1.8 V < VIN < VUVLO√
Power supply removalVIN < 1.8 Vundefined
The PG pin has a 34-μs delay time on the falling edge and a 34-μs delay before PG goes high. See Figure 8-3.
Figure 8-3 Power-Good Transient and Delay Behavior