SLWS181K October   2005  – December 2015 TRF3761-A , TRF3761-B , TRF3761-C , TRF3761-E , TRF3761-F , TRF3761-G , TRF3761-H , TRF3761-J

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Recommended Operating Conditions
    3. 7.3  Thermal Information
    4. 7.4  Electrical Characteristics
    5. 7.5  Electrical Characteristics, TRF3761-A
    6. 7.6  Electrical Characteristics,TRF3761-B
    7. 7.7  Electrical Characteristics, TRF3761-C
    8. 7.8  Electrical Characteristics, TRF3761-D
    9. 7.9  Electrical Characteristics, TRF3761-E
    10. 7.10 Electrical Characteristics, TRF3761-F
    11. 7.11 Electrical Characteristics, TRF3761-G
    12. 7.12 Electrical Characteristics, TRF3761-H
    13. 7.13 Electrical Characteristics, TRF3761-J
    14. 7.14 Timing Requirements
    15. 7.15 Typical Characteristics
      1. 7.15.1 Typical Characteristics, TRF3761-A (See )
      2. 7.15.2 Typical Characteristics, TRF3761-B (See )
      3. 7.15.3 Typical Characteristics, TRF3761-C (See )
      4. 7.15.4 Typical Characteristics, TRF3761-D (See )
      5. 7.15.5 Typical Characteristics, TRF3761-E (See )
      6. 7.15.6 Typical Characteristics, TRF3761-F (See )
      7. 7.15.7 Typical Characteristics, TRF3761-G (See )
      8. 7.15.8 Typical Characteristics, TRF3761-H (See )
      9. 7.15.9 Typical Characteristics, TRF3761-J (See )
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VCO
      2. 8.3.2  Divide by 2, by 4, and Output Buffer
      3. 8.3.3  N-Divider
        1. 8.3.3.1 Prescaler Stage
        2. 8.3.3.2 A and B Counter Stage
        3. 8.3.3.3 Reference Divider
      4. 8.3.4  Phase Frequency Detector (PFD) and Charge Pump Stage
      5. 8.3.5  Mux Out
      6. 8.3.6  Div 1/2/4
      7. 8.3.7  Serial interface
      8. 8.3.8  CHIP ENABLE
      9. 8.3.9  Buffer Power Down
      10. 8.3.10 External VCO IN
    4. 8.4 Device Functional Modes
      1. 8.4.1 Programmable Divider Mode
    5. 8.5 Programming
      1. 8.5.1 Serial Interface Programming Registers Definition
    6. 8.6 Register Maps
      1. 8.6.1 Register 1
      2. 8.6.2 Register 2
      3. 8.6.3 Register 3
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Loop Filter Design
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Loop Filter Design Example
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Initial Calibration and Frequency Setup at Power Up
          1. 9.2.2.1.1 Register 1
          2. 9.2.2.1.2 Register 2
          3. 9.2.2.1.3 Register 3
        2. 9.2.2.2 Re-Calibration After Power Up
        3. 9.2.2.3 Synthesizing a Selected Frequency
      3. 9.2.3 Application Curve
      4. 9.2.4 Application Example for a High Performance RF Transmit Signal Chain
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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発注情報

8 Detailed Description

8.1 Overview

TRF3761 is an integrated frequency synthesizer with low-noise, voltage-controlled oscillator (VCO) and an integer-N PLL. N-Divider block supports flexible output frequency range. A 3-wire serial-programming interface (SPI) interface is used to control the device. Device also supports power down feature through SPI interface or via chip_en pin.

8.2 Functional Block Diagram

TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K fbd_slws181.gif

8.3 Feature Description

8.3.1 VCO

The TRF3761 integrates a high-performance, LC tank, voltage-controlled oscillator (VCO). For each of the devices of the TRF3761 family, the inductance and capacitance of the tank are optimized to yield the best phase-noise performance. The VCO output is fed externally and to the prescaler through a series of very low noise buffers, that greatly reduce the effect of load pulling onto the VCO.

8.3.2 Divide by 2, by 4, and Output Buffer

To extend the frequency coverage, the TRF3761 integrates a divide by 2 and by 4 with a low noise floor. The VCO signal is fed externally through a final open-collector differential-output buffer. This buffer is able to provide up to 3dBm (typical) of power into a 200Ω differential resistive load. The open-collector structure gives the flexibility to choose different load configurations to meet different requirements.

8.3.3 N-Divider

8.3.3.1 Prescaler Stage

This stage divides down the VCO frequency before the A and B counters. This is a dual-modulus prescaler and the user can select any of the following settings: 8/9, 16/17, 32/33, and 64/65. Prescaling is used due to the fact that the internal devices are limited in frequency operations of 200MHz. To determine the proper prescaler value, Fout which is the frequency out of the VCO is divided by the numerator of the prescaler if the answer is less than 200 MHz then that is the prescalar to use, see Equation 1. If the value is higher than 200 MHz then repeat this procedure with the next prescalar numerator until a value of 200MHz or less is achieved. Refer to Synthesizing a Selected Frequency.

Equation 1. TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K q_fout_lws181.gif

8.3.3.2 A and B Counter Stage

The TRF3761 includes a 6-bit A counter and a 13-bit B counter that operate on the output of the prescaler. The A counter can take values from 0 to 63, while the B counter can take values from 3 to 8191. Also, the value for the B counter must be greater than or equal to the value for the A counter. The A and B counter with the prescaler stage create the VCO N-divider, see Equation 2 and Equation 3. Refer to Synthesizing a Selected Frequency.

Equation 2. TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K q_n_lws181.gif
Equation 3. TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K q_n_pre_lws181.gif

8.3.3.3 Reference Divider

TRF3761 includes a 14-bit RDiv, also known as RDiv, that allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector (PFD) this clock is also known as FPFD which is also the channel step size. Division ratios from 1 to 16,383 are allowed. To determine RDiv use Equation 4.

Equation 4. TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K q_rdiv_lws181.gif

The output frequency (Fout) is determined using Equation 5.

Equation 5. TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K q_fout_fpfd_lws181.gif

8.3.4 Phase Frequency Detector (PFD) and Charge Pump Stage

The outputs of the RDiv and the N counter are fed into the PFD stage, where the two signals are compared in frequency and phase. The TRF3761 features an anti-backlash pulse, whose width is controllable by the user through the serial programming interface. The PFD feeds the charge pump, whose output current pulses are fed into an external loop filter, which eventually produces the tuning voltage needed to control the integrated VCO to the desired frequency.

8.3.5 Mux Out

MUX_OUT pin (39) provides a communication port to the microcontroller circuit. See Table 4 in the Detailed Design Procedure section.

8.3.6 Div 1/2/4

Div 1/2/4 is the frequency divider for the TRF3761. This circuit can be programmed thru the serial programming interface (SPI) to divide the output frequency of the VCO by 1, 2 or 4. This feature allows for the same loop filter design to be used for any of the 3 divide by modes, 1, 2 and 4. For example, if the VCO is running at 1499MHz to 1608MHz band then with the same exact circuit, run the output in the divide by 2 mode 749.5MHz to 804MHz band or in the divide by 4 mode 374.75MHz to 402MHz.

8.3.7 Serial interface

The programming interface pins (3, 4, 5) to the chip are the serial programming interface (SPI). The interface requires a Clock, Data, and Strobe signal to operate. See timing diagram Figure 83.

8.3.8 CHIP ENABLE

This feature provides a way to shut down the chip when not needed in order to conserve power. CHIP_EN Pin (2) needs to be High for normal operation.

8.3.9 Buffer Power Down

PD_OUTBUFF pin (1), when enabled in software can provide a -40dB reduction in the output power while the VCO is locked and running. This feature is to help with isolation between RX and TX.

8.3.10 External VCO IN

EXT_VCO_IN pin (18) allows for the use of an external VCO to use the phase lock loop circuit in the TRF3761. This feature enables higher frequencies to be synthesized.

8.4 Device Functional Modes

8.4.1 Programmable Divider Mode

TRF3761 frequency range is extended by integrating a divide by 2 and by 4 options. The VCO signal is fed externally through differential-output buffer. The divider block allows to divide the output frequency of the VCO by 1, 2 or 4 by programming thru serial programming interface (SPI). These 3 divide by modes of 1, 2 and 4 enables the usage of same loop filter for wider frequency coverage.

8.5 Programming

8.5.1 Serial Interface Programming Registers Definition

The TRF3761 features a 3-wire serial programming interface that controls an internal, 32-bit shift register. There are a total of 3 signals that need to be applied: the CLOCK (pin 3), the serial DATA (pin 4) and the STROBE (pin 5). The DATA (DB0-DB31) is loaded LSB first and is read on the rising edge of the CLOCK. The STROBE is asynchronous to the CLOCK and at its rising edge the data in the shift register gets loaded onto the selected internal register. The first four bits (DB0-DB3) is the address to select the available internal registers.

TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K tim_dia_lws181.gif
A. The first 4 bits, DB(3-0), of data are Address bits. The 28 remaining bits, DB(31-4), are part of the command. The command is little endian or lower bits first.
Figure 83. Serial Programming Timing Diagram

8.6 Register Maps

8.6.1 Register 1

Figure 84. Register 1: Device Setup
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16
Full Cal Req CP_TEST TRIS_CP PFD_POL Anti Backlash Reference Clock Divider (RDiv)
R/W R/W R/W R/W R/W R/W
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Reference Clock Divider (RDiv) PD BUFOUT OUTBUF EN_SEL Output Mode Charge Pump Current Select REST Register Address
R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 1. Register 1: Device Setup

REGISTER 1 MAPPING
Data Field DB31 FULL_CAL_REQ This is a read only bit, that indicates if a power-up cal is required 0 power-up cal is not required
1 power-up cal is required
DB30 CP_TEST TI internal use only 1 test enabled
DB29 TRIS_CP High-impedance state charge pump output 1 CP high-impedance state
0 for normal operation
DB28 PFD_POL Selects Polarity of PFD, should match polarity of VCO gain. If using external VCO with Negative gain then set to 0 and vise versa. The internal VCO has positive gain so set to positve(1) 0 negative
1 positive
DB27 ABPW1 ABPW<1,0>: anti-backlash pulse width 00 1.5ns delay
01 0.9ns delay
10 3.8ns delay
11 2.7ns delay
DB26 ABPW0
DB25 RDIV_13 14-bit reference clock divider RDIV<13,0>:00...01: divide by 1
RDIV<13,0>:00...10: divide by 2
RDIV<13,0>:00...11: divide by 3
DB24 RDIV_12
DB23 RDIV_11
DB22 RDIV_10
DB21 RDIV_9
DB20 RDIV_8
DB19 RDIV_7
DB18 RDIV_6
DB17 RDIV_5
DB16 RDIV_4
DB15 RDIV_3
DB14 RDIV_2
DB13 RDIV_1
DB12 RDIV_0
DB11 PD_BUFOUT If DB10 = 0 then it controls power down of output buffer <DB10:11>:
00 default; output buffer on
01 output buffer off
1x output buffer on/off controlled by OUTBUF_EN pin
DB10 OUTBUF_EN_SEL Select Output Buffer enable control: 0 internal
1 through OUTBUF_EN pin
DB9 OUT_MODE_1 OUTBUFMODE<1,0>: Selection of RF output buffer division ratio 00 divide by 1
01 divide by 2
10 divide by4
DB8 OUT_MODE_0
DB7 ICP2 ICP<2,0>: select charge pump current (1 mA step). From 1.4mA to 11.2mA with Rbias set to 2.37Kohms.
DB6 ICP1
DB5 ICP0
DB4 RESET Registers reset 1 high
0 low for normal operation
Address Bits DB3 Address Bits <3,0>=0000 for register 1
DB2
DB1
DB0

OUT_MODE<1,0>: TRF3761 has an optional divide by 2 or 4 output, which is selectable by programming bits <OUT_MODE_1, OUT_MODE_0> of register 1 (see Table 1).

CP_TEST: By setting bit DB30 to 1 it is possible to test the PFD up or down pulses. Internal TI use only.

TRIS_CP: If bit DB29 is set to 1, the charge pump output goes in tri-state. For normal operation, DB29 must be set to 0.

ABPW: Bits <DB27, DB26> are used to program the width of the anti-backlash pulses of the PFD. The user selects one of the following values: 0.9ns, 1.5ns, 2.7ns and 3.8ns. Backlash can occur when Fpfd becomes phase aligned with Fout of the VCO. This will cause a high impedance state on the phase detector and allow the output frequency to drift until the phase difference is enough to cause the phase detector to start sending signals to the charge pump to correct the difference. This slight variation will show up as a sub harmonic of the pfd signal in the passband of the loop filter which would result in a significant spur in the output of the VCO. It is recommended that the anti-backlash pulse be set to the 1.5ns which gives the best spur reduction for the TRF3761.

PFD_POL: Bit DB28 of register 1 sets the polarity of the PFD. A Low (0) selects a negative polarity, and a High (1) selects a positive polarity. By choosing the correct polarity, the TRF3761 will works with an external VCO having both positive and negative gain (Kv). For example if an external VCO has a Kv = –23MHz/V then the PFD polarity would need to be negative, so DB28 would be set to a Low (0). When using the internal VCO with a Kv of 23MHz/V, the PDF_POL should be set to 1.

RDiv: A 14-bit word programs the RDiv for the reference signal, DB25 is the MSB and DB12 is the LSB. RDiv value is determined by dividing the reference frequency by the channel step size. For example if the reference frequency is 10MHz and the channel step size is 200KHz then RDiv would be 50. This sets up the Fpfd for the phase detector, in other words the reference frequency will be divided down by a factor of RDiv which in this example is 50.

ICP: Bits <DB7, DB5> set the charge pump current.

Equation 6. TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K q_icp_lws181.gif

which reduces to:

Equation 7. TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K q_icp2_lws181.gif

where N = decimal value of [Reg1 DB<7:5>]. The range is set by N and Rbias2. It is recommended that Icp be set to 7mA or <DB7, DB5>=101.

OUTBUF_EN_SEL: Output buffer on/off state is controlled through serial interface or an external pin. If bit DB10 is a 0 (default state) the output buffers state is elected through bit DB11. If DB10 is a 1, the buffers on/off are directly controlled by the OUTBU_EN pin.

RESET: Setting bit DB4 to 1, all registers are reset to default values.

Refer to Register 1 under the Detailed Design Procedure section.

8.6.2 Register 2

Figure 85. Register 2: VCO Calibration
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16
START_CAL VCO Frequency in MHz Reference Frequency Continued
R/W R/W R/W
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Reference Frequency (Fractional Part) Reference Frequency (Integer Part) Register Address
R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 2. Register 2: VCO Calibration

REGISTER 2 MAPPING
Data Field DB31 START_CAL 1 start calibration
DB30 FOUT12 VCO frequency in MHz start calibration
DB29 FOUT11
DB28 FOUT10
DB27 FOUT9
DB26 FOUT8
DB25 FOUT7
DB24 FOUT6
DB23 FOUT5
DB22 FOUT4
DB21 FOUT3
DB20 FOUT2
DB19 FOUT1
DB18 FOUT0
DB17 REF_FRAC6 Reference frequency in MHz (fractional part) 0000000 = 0.00MHz
0000001 = 0.01MHz
0000010 = 0.02MHz
. . . . .
1100011 = 0.99MHz
DB16 REF_FRAC5
DB15 REF_FRAC4
DB14 REF_FRAC3
DB13 REF_FRAC2
DB12 REF_FRAC1
DB11 REF_FRAC0
DB10 REF6 Reference frequency in MHz (integer part) 0001010 =10MHz
0001011 =11MHz
. . . . .
1101000 = 104MHz
DB9 REF5
DB8 REF4
DB7 REF3
DB6 REF2
DB5 REF1
DB4 REF0
Address Bits DB3 0 Address Bits <3,0>=0001 for register 2
DB2 0
DB1 0
DB0 1

Reference Frequency: The 14 bits <DB17, DB4> are used to specify the input reference frequency as multiples of 10kHz. Bits <DB10,DB4> specify the integer part of the reference frequency expressed in MHz. Bits <DB17,DB11> set the fraction part. Those values are then used during the calibration of the internal VCO. For example if using a 20MHz reference oscillator then bits<DB10,DB4> would be 0010100 and bits<DB17,DB11> would be 0000000. If the reference oscillator is 13.1MHz then bits<DB10,DB4> would be 0001101 and bits<DB17,DB11> would be 0001010.

Start Calibration: A 1 in DB31 starts the internal VCO calibration. When the calibration is complete, DB31 bit is internally reset to 0.

FOUT<12,0>: This 13-bit word <DB30,DB18> specifies the VCO output frequency in MHz. If output frequency is not a integer multiple of MHz, this value must be approximated to the closest integer in MHz.

Refer to Register 2 under the Detailed Design Procedure section.

8.6.3 Register 3

Figure 86. Register 3: A and B Counters
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16
RSRV RSRV Lock PLL Test MUX B-Counter
R/W R/W R/W R/W R/W
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
B-Counter A-Counter Dual-Modulus Prescalar Mode Register Address
R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 3. Register 3: A and B Counters

REGISTER 3 MAPPING
Data Field DB31 Rsrv Reserved
DB30 Rsrv Reserved
DB29 START_LK Lock PLL to frequency 1 active
DB28 TEST_MUX_3 See Table 4 for descriptions and settings. 0001 = LOCK_DETECT enabled
DB27 TEST_MUX_2
DB26 TEST_MUX_1
DB25 TEST_MUX_0
DB24 B_12 13-bit B counter
DB23 B_11
DB22 B_10
DB21 B_9
DB20 B_8
DB19 B_7
DB18 B_6
DB17 B_5
DB16 B_4
DB15 B_3
DB14 B_2
DB13 B_1
DB12 B_0
DB11 A_5 6-bit A counter
DB10 A_4
DB9 A_3
DB8 A_2
DB7 A_1
DB6 A_0
DB5 PRESC_MOD1 Dual-modulus prescaler mode <B5,B4>:00 for 8/9
<B5,B4>:01 for 16/17
<B5,B4>:10 for 32/33
<B5,B4>:11 for 64/65
DB4 PRESC_MOD0
Address Bits DB3 0 Address Bits <3,0>=0010 for register 3
DB2 0
DB1 1
DB0 0

B<12,0>: This 13-bit word <DB24,DB12> controls the value of the B counter of the N divider. The valid range is from 3 to 8191.

A<5,0>: These 6 bits <DB11,DB6> control the value of the A counter. The valid range is from 0 to 63.

PRESC_MOD<1,0>: These bits <DB5,DB4> define the mode of the dual-modulus prescaler according to Table 3.

START_LK: TRF3761 does not load the serial interface registers values into the dividers registers until bit DB29 of register 3 is set to 1. After TRF3761 is locked to the new frequency, bit DB29 is internally reset to 0.

Refer to Register 3 under the Detailed Design Procedure section.