JAJSO45A August   2023  – September 2023 UCC14130-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Insulation Specifications
    6. 7.6 Electrical Characteristics
    7. 7.7 Safety Limiting Values
  9. 8 Safety-Related Certifications
  10. 9 Insulation Characteristics
  11. 10Typical Characteristics
  12. 11Detailed Description
    1. 11.1 Overview
    2. 11.2 機能ブロック図
    3. 11.3 Feature Description
      1. 11.3.1 Power Stage Operation
        1. 11.3.1.1 VDD-VEE Voltage Regulation
        2. 11.3.1.2 COM-VEE Voltage Regulation
        3. 11.3.1.3 Power Handling Capability
      2. 11.3.2 Output Voltage Soft Start
      3. 11.3.3 ENA and PG
      4. 11.3.4 Protection Functions
        1. 11.3.4.1 Input Undervoltage Lockout
        2. 11.3.4.2 Input Overvoltage Lockout
        3. 11.3.4.3 Output Undervoltage Protection
        4. 11.3.4.4 Output Overvoltage Protection
        5. 11.3.4.5 Overpower Protection
        6. 11.3.4.6 Overtemperature Protection
    4. 11.4 Device Functional Modes
  13. 12Application and Implementation
    1. 12.1 Application Information
    2. 12.2 Typical Application
      1. 12.2.1 Design Requirements
      2. 12.2.2 Detailed Design Procedure
        1. 12.2.2.1 Capacitor Selection
        2. 12.2.2.2 Single RLIM Resistor Selection
        3. 12.2.2.3 RDR Circuit Component Selection
        4. 12.2.2.4 Feedback Resistors Selection
    3. 12.3 System Examples
  14. 13Power Supply Recommendations
  15. 14Layout
    1. 14.1 Layout Guidelines
    2. 14.2 Layout Example
  16. 15デバイスおよびドキュメントのサポート
    1. 15.1 ドキュメントのサポート
      1. 15.1.1 関連資料
    2. 15.2 ドキュメントの更新通知を受け取る方法
    3. 15.3 サポート・リソース
    4. 15.4 商標
    5. 15.5 静電気放電に関する注意事項
    6. 15.6 用語集
  17. 16Mechanical, Packaging, and Orderable Information
  18. 17Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions


GUID-55658DE4-B3D2-4489-ADBD-3A077C4B7E80-low.svg

Figure 6-1 DWN Package, 36-Pin SSOP (Top View)
Table 6-1 Pin Functions
PINTYPE (1)DESCRIPTION
NAMENO.
GNDP1, 2, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18GPrimary-side ground connection for VIN. PIN 1,2, and 5 are analog ground. PIN 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, and 18 are power ground. Place several vias to copper pours for thermal relief. See Layout Guidelines section.
PG3O

Active low power-good open-drain output pin. PG remains low when (VVIN_UVLOP ≤ VVIN ≤ VVIN_OVLOP); (VVDD_UVP ≤ VFBVDD ≤ VVDD_OVP); (VVEE_UVP ≤ VFBVEE ≤ VVEE_OVP); TJ_Primary ≤ TSHUTPPRIMARY_RISE; and TJ_secondary ≤ TSHUTSSECONDARY_RISE

ENA4IEnable pin. Forcing ENA LOW disables the device. Pull HIGH to enable normal device functionality. 5.5-V recommended maximum.
VIN6, 7P

Primary input voltage. PIN 6 is for analog input, and PIN 7 is for power input. For PIN 7, connect two 10-µF ceramic capacitor from power VIN PIN 7 to power GNDP PIN 8. Connect a 0.1-µF high-frequency bypass ceramic capacitor close to PIN 7 and PIN 8.

VEE19, 20, 21, 22, 23, 24, 25,26, 27, 30,31, 36G

Secondary-side reference connection for VDD and COM. The VEE pins are used for the high current return paths.

VDD28, 29P

Secondary-side isolated output voltage from transformer. Connect a 10-µF and a parallel 0.1-µF ceramic capacitor from VDD to VEE. The 0.1-µF ceramic capacitor is the high frequency bypass and must be next to the IC pins.

RLIM32PSecondary-side second isolated output voltage resistor to limit the source current from VDD to COM node, and the sink current from COM to VEE. Connect a resistor from RLIM to COM to regulate the (COM – VEE) voltage. See RLIM Resistor Selection for more detail.
FBVEE33IFeedback (COM – VEE) output voltage sense pin used to adjust the output (COM – VEE) voltage. Connect a resistor divider from COM to VEE so that the midpoint is connected to FBVEE, and the equivalent FBVEE voltage when regulating is 2.5 V. Add a 330-pF ceramic capacitor for high frequency decoupling in parallel with the low-side feedback resistor. The 330-pF ceramic capacitor for high frequency bypass must be next to the FBVEE and VEEA IC pins on top layer or back layer connected with vias.
FBVDD34IFeedback (VDD – VEE) output voltage sense pin and to adjust the output (VDD – VEE) voltage. Connect a resistor divider from VDD to VEE so that the midpoint is connected to FBVDD, and the equivalent FBVDD voltage when regulating is 2.5 V. Add a 330-pF ceramic capacitor for high frequency decoupling in parallel with the low-side feedback resistor. The 330-pF ceramic capacitor for high frequency bypass must be next to the FBVDD and VEEA IC pins on top layer or back layer connected with vias.
VEEA35GSecondary-side analog sense reference connection for the noise sensitive analog feedback inputs, FBVDD and FBVEE. Connect the low-side feedback resistors and high frequency decoupling filter capacitor close to the VEEA pin and respective feedback pin FBVDD or FBVEE. Connect to secondary-side gate drive lowest voltage reference, VEE. Use a single point connection and place the high frequency decoupling ceramic capacitor close to the VEEA pin. See Layout Guidelines section.
(1) P = power, G = ground, I = input, O = output