Designing with the UCC1413x-Q1 module is simple. First, choose single output or dual output. Determine the voltage for each output and then set the regulation through resistor dividers. Second, select the recommended input and output capacitors according to the procedure in the section of capacitor selection. The gate charge of the power device determines the amount of output decoupling capacitance needed at the gate driver input. Third, calculate the R_LIM resistor value for regulating the (COM – VEE) voltage rail for a dual output according to the procedure in the section of R_LIM or RDR selection.

For the dual output configuration, the VDD-to-VEE output capacitor placement and the RLIM-to-COM resistance introduce great impact to the power module performance and system BOM cost. Table 12-1 compares four combinations of two different VDD-to-VEE output decoupling capacitor placements and two R_LIM current-limit networks. The number 1 ranking represents the best, and the number 4 means the worst. The table indicates that case B offers the best performance and case A offers the lowest BOM cost. As shown in Figure 12-8, C_OUT1 is the decoupling capacitor closest to VDD and VEE pins, while C_OUT1B is the decoupling capacitor closest to the output load. Besides, the current-limit resistor network between RLIM pin and COM terminal is called the RDR circuitry, which can program the charge and discharge current of R_LIM regulator independently.

For the gate driver application with high di/dt current change as example, the finite impedance between the output terminal of power modules and the input bias terminal of output load greatly affects the transient response at the point of load, so the local decoupling capacitor C_OUT1B provides a very effective low-impedance decoupling for both V_VDD-to-COM and V_COM-to-VEE in the driver switching condition. From the schematic aspect, it seems that adding C_OUT1B means one more extra capacitor, but the reality is that it helps to avoid the need of oversizing C_OUT2 and C_OUT3. With C_OUT1B, the reduced capacitance and capacitor body size for C_OUT2 and C_OUT3 end up a reduced total BOM cost on output capacitor bank. The following Section 12.2.2.1 will describe the design procedure of C_OUT1B for more detail. Another benefit is that when capacitance of C_OUT2 and C_OUT3 is reduced, a higher R_LIM resistance can be used for COM-to-VEE regulation, so the power loss of RLIM regulator is reduced for higher power module efficiency.

As shown in Figure 12-8, the RDR circuitry is a current-limit resistor network of the RLIM pin to allow R_LIM regulator to optimize the charge and discharge current capabilities independently for further increasing the power module efficiency from the reduced power loss of R_LIM regulator. The circuity consists of three components, one high-resistance resistor R_LIM1 in parallel with another resistor-diode branch, a small-resistance resistor R_LIM2 in series with a small-signal diode D_LIM. R_LIM1 resistance is much higher than R_LIM2 resistance. Since V_VDD-to-VEE is usually much higher than V_COM-to-VEE especially in gate drive application, R_LIM1 provides a high-resistance path for the internal charge switch to greatly reduce the switch current, so as to reduce the switching loss and conduction loss of the internal charge switch as well as the power loss of R_LIM1 for higher efficiency. In addition, with a smaller charge current, the disturbance to V_VDD-to-VEE ripple dipping effect at the charge switch turn-on instance will be minimized, so the total peak-to-peak ripple is reduced.

When the discharge switch turns on, the D_LIM provides a unidirectional path to divert most of the RLIM-pin current back to R_LIM2. This approach allows the RLIM regulator equipped with strong enough sinking capability to avoid the unbalanced current at COM-pin terminal from charging up V_COM-to-VEE away from regulation band. Since V_COM-to-VEE is lower than V_VDD-to-VEE such as -5V respect to 25V as example, the power loss of the internal discharge switch and R_LIM2 with larger switching current is less concern. On the contrary, if only one resistor is used to the RLIM pin, the resistor needs to design for worst case with lowest resistance to ensure V_COM-to-VEE regulation, so the efficiency will be compromised. For example, the RDR circuitry with R_LIM1 of 1kΩ and R_LIM2 of 51Ω can increase the converter efficiency 7% higher with 10mA load from VDD to COM and reduce the case temperature 10°C, compared with using one R_LIM of 51Ω only.

Based on above, Case B is highly recommended as first choice in application. User can still use other thee design cases for other considerations. The design calculator provides a generic calculation tool to help user optimize each. The equations are based on the below detail descriptions.