JAJSQ36A april   2023  – august 2023 UCC14241-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Insulation Specifications
    6. 7.6 Electrical Characteristics
    7. 7.7 Safety Limiting Values
  9. 8 Safety-Related Certifications
  10. 9 Insulation Characteristics
  11. 10Typical Characteristics
  12. 11Detailed Description
    1. 11.1 Overview
    2. 11.2 Functional Block Diagram
    3. 11.3 Feature Description
      1. 11.3.1 Power Stage Operation
        1. 11.3.1.1 VDD-VEE Voltage Regulation
        2. 11.3.1.2 COM-VEE Voltage Regulation
        3. 11.3.1.3 Power Handling Capability
      2. 11.3.2 Output Voltage Soft Start
      3. 11.3.3 ENA and PG
      4. 11.3.4 Protection Functions
        1. 11.3.4.1 Input Undervoltage Lockout
        2. 11.3.4.2 Input Overvoltage Lockout
        3. 11.3.4.3 Output Undervoltage Protection
        4. 11.3.4.4 Output Overvoltage Protection
        5. 11.3.4.5 Overpower Protection
        6. 11.3.4.6 Overtemperature Protection
    4. 11.4 Device Functional Modes
  13. 12Application and Implementation
    1. 12.1 Application Information
    2. 12.2 Typical Application
      1. 12.2.1 Design Requirements
      2. 12.2.2 Detailed Design Procedure
        1. 12.2.2.1 Capacitor Selection
        2. 12.2.2.2 Single RLIM Resistor Selection
        3. 12.2.2.3 RDR Circuit Component Selection
        4. 12.2.2.4 Feedback Resistors Selection
      3. 12.2.3 Application Curves
    3. 12.3 System Examples
    4. 12.4 Power Supply Recommendations
    5. 12.5 Layout
      1. 12.5.1 Layout Guidelines
      2. 12.5.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 用語集
  15. 14Mechanical, Packaging, and Orderable Information
  16. 15Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

12.2.3 Application Curves

The PMP23223 is a reference design that pairs the complementary UCC14240-Q1 isolated DC/DC power module with the UCC21732-Q1 isolated gate driver for a SiC power MOSFET or IGBT power module. The following waveforms show the controlled soft start for both positive and negative rails. Also shown, is the fast and highly accurate voltage regulation during gate driver switching from 1 kHz to 35 kHz. See PMP23223 reference design test report for more details.

GUID-20220505-SS0I-CBW3-DS7N-76FHFCT21RKG-low.pngFigure 12-11 Power-Up Sequence.
GUID-20220505-SS0I-KQ3C-FQFJ-QVWSNTLDC0GJ-low.pngFigure 12-13 Ripple voltage: VDD-VEE Switching 100-nF Load at 1 kHz.
GUID-20220505-SS0I-SSPN-9GZ6-TFJSHTJFJNPD-low.pngFigure 12-15 Ripple voltage: VDD-VEE Switching 100-nF Load at 35 kHz.
GUID-20220505-SS0I-4P7K-55D4-P6PDQRF0JJ7M-low.pngFigure 12-17 Gate Waveform Switching 100 nF at 35kHz.
GUID-20220505-SS0I-WKZC-FNH4-FQ3HTPJSCHCR-low.pngFigure 12-12 Ripple voltage: VEE-COM Switching 100-nF Load at 1 kHz.
GUID-20220505-SS0I-66JQ-GZTQ-L3KPD1FLDBPR-low.pngFigure 12-14 Ripple voltage: VEE-COM Switching 100-nF Load at 35 kHz.
GUID-20220505-SS0I-RWGG-3HN4-D924GSSVCVCD-low.pngFigure 12-16 Gate Waveform Switching 100 nF at 1 kHz.