JAJSQ36A april   2023  – august 2023 UCC14241-Q1

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Revision History
  6. Device Comparison
  7. Pin Configuration and Functions
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Insulation Specifications
    6. 7.6 Electrical Characteristics
    7. 7.7 Safety Limiting Values
  9. Safety-Related Certifications
  10. Insulation Characteristics
  11. 10Typical Characteristics
  12. 11Detailed Description
    1. 11.1 Overview
    2. 11.2 Functional Block Diagram
    3. 11.3 Feature Description
      1. 11.3.1 Power Stage Operation
        1. 11.3.1.1 VDD-VEE Voltage Regulation
        2. 11.3.1.2 COM-VEE Voltage Regulation
        3. 11.3.1.3 Power Handling Capability
      2. 11.3.2 Output Voltage Soft Start
      3. 11.3.3 ENA and PG
      4. 11.3.4 Protection Functions
        1. 11.3.4.1 Input Undervoltage Lockout
        2. 11.3.4.2 Input Overvoltage Lockout
        3. 11.3.4.3 Output Undervoltage Protection
        4. 11.3.4.4 Output Overvoltage Protection
        5. 11.3.4.5 Overpower Protection
        6. 11.3.4.6 Overtemperature Protection
    4. 11.4 Device Functional Modes
  13. 12Application and Implementation
    1. 12.1 Application Information
    2. 12.2 Typical Application
      1. 12.2.1 Design Requirements
      2. 12.2.2 Detailed Design Procedure
        1. 12.2.2.1 Capacitor Selection
        2. 12.2.2.2 Single RLIM Resistor Selection
        3. 12.2.2.3 RDR Circuit Component Selection
        4. 12.2.2.4 Feedback Resistors Selection
      3. 12.2.3 Application Curves
    3. 12.3 System Examples
    4. 12.4 Power Supply Recommendations
    5. 12.5 Layout
      1. 12.5.1 Layout Guidelines
      2. 12.5.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 用語集
  15. 14Mechanical, Packaging, and Orderable Information
  16. 15Tape and Reel Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Capacitor Selection

The UCC14241-Q1 device creates an isolated output VDD-VEE as its main output. The device also creates a second output COM-VEE, using VDD-VEE as its power source. Because both outputs are isolated from the input, and sharing VEE as the common reference point, the UCC14241-Q1 outputs can be configured as dual-output two-positive, dual-output two-negative, or dual-output one-positive and one-negative. UCC14241-Q1 output can also be used as a single positive output or single negative output.

When the module is configured as dual-output, one-positive output, one-negative output; it is very important to properly select the output capacitor ratios COUT2 and COUT3 to optimize the regulation and avoid causing an over-voltage or under-voltage fault.

Table 12-2 Calculated Capacitor Values
CAPACITORVALUE (µF)NOTES
CIN

10 + 0.1

Place a 10-μF and a 0.1-μF high-frequency decoupling capacitor in parallel close to VIN pins. A capacitance greater than 10 uF can be used to reduce the voltage ripple when the series impedance from the voltage source to the VIN pins is large.
COUT12.2+ 0.1Add a 2.2-μF and a 0.1-μF capacitor for high-frequency decoupling of (VDD – VEE). Place close to the VDD and VEE pins. A capacitance greater than 2.2 uF can be used to reduce the output voltage ripple.

COUT1B

See below

Bulk charge, decoupling output capacitors are required to be located next to the gate driver pins. The COUT2 and COUT3 capacitance ratio is important to optimize the dual output voltage divider accuracy during charge or discharge switching cycles; while the COUT1B capacitor is used to minimize the total capacitance including COUT1B, COUT2, and COUT3 capacitance values.
COUT2

See below

COUT3See below

Output capacitor decoupling is important for optimal gate driver operation. Best high frequency decoupling can be achieved by reducing the parasitic impedance in the charge/discharge path. Using ceramic capacitors with low ESR and low ESL are important, as well as minimizing the trace impedance.

As described in Figure 12-3, a decoupling capacitor COUT1 is required at the VVDD-VEE output pins of the UCC14241-Q1 for high frequency decoupling. COUT2 and COUT3 however, are needed at the gate driver pins for VVDD-COM and VVEE-COM decoupling. The impedance between COUT1 and the COUT2/COUT3 combo prevents the COUT1 from assisting the high frequency decoupling of the gate driver, requiring the COUT2 and COUT3 to take on the full load. The impedance may be contributed from the PCB traces, socket connections, EMI filters, or ferrite beads etc. This causes the COUT2 and in particular the COUT3 to get relatively large achieve a small voltage droop.

GUID-EF609F68-2527-4FE7-A52A-D677B44940E0-low.svgFigure 12-3 Dual Output Schematic with Cout1, Cout2, and Cout3

The required COUT2 and COUT3 capacitance can be reduced by introducing a COUT1B capacitor from VVDD-VEE at the gate driver pins next to COUT2 and COUT3 as shown in Figure 12-4. The COUT1B assists with the decoupling total capacitance for both COUT2 and COUT3; thereby reducing the total capacitance (COUT1B + COUT2 +COUT3) needed to achieve the desired voltage droop. Figure 12-5 shows that as COUT1B is increased from “none” to higher COUT1B values, there is a significant reduction in COUT2 and COUT3 and reduction of the total net capacitance, until a point of diminishing returns is reached (a “knee” point) where any additional COUT1B will have a relatively small reduction of COUT2 and COUT3, and starts more significantly increasing the total net capacitance. The optimal COUT1B, COUT2, and COUT3 at the minimum total net capacitance benefit both output capacitor size reduction and BOM cost reduction.

GUID-1198DE24-E7D7-420E-ACF8-6F7A0D77C452-low.svgFigure 12-4 Dual Output Schematic with Cout1, Cout1B, Cout2, and Cout3

GUID-52DDDFB0-BB6C-4618-A259-F89722F975B3-low.pngFigure 12-5 Output Capacitance variation with Cout1B selection

To calculate COUT1B, COUT2, and COUT3, we calculate the equivalent (VDD-COM) capacitance, which is equal to the series capacitance of COUT1B and COUT3 in parallel with COUT2. This equivalent (VDD-VEE) capacitance will be sized to limit the predetermined (VDD-COM) discharge voltage drop when the power switch (SiC or IGBT) gate charge is turned-on.

Equation 1. CVDD-COMEQ=COUT1B×COUT3COUT1B+COUT3+COUT2
Solving for acceptable voltage droop on VVDD-COM from the load transient, ∆V(VDD-COM)_droop,
Equation 2. CVDD-COMEQ=QgV(VDD-COM)_droop

The COUT2 over COUT3 ratio is defined as a coefficient of K23,which is the multiplication of a voltage divider ratio along with a ratio of differential current. The voltage divider ratio is from the series configuration of the two capacitors. The current divider ratio is calculated based on the charge current through the two capacitors. IMAX_POWER is the maximum instantaneous current from the power module during the burst on-time, which can be obtained from dividing the maximum power on the datasheet SOA curve at TA of 25°C by VVDD-VEE. IVDD-COM is the total quiescent current between VDD and COM. For gate driver as example, IVDD-VEE is the current consumption without switching. ICOM-VEE is the total quiescent current between COM and VEE. Based on KCL, the differential current charging up COUT2 during the burst on-time is (IMAX_POWER - IVDD-COM), and the one charging up COUT3 is (IMAX_POWER - ICOM-VEE).

Equation 3. COUT3=COUT2×K23

where

Equation 4. K23=V(VDD-COM)×IMAX_POWER-ICOM-VEEV(COM-VEE)×IMAX_POWER-IVDD-COM

Next, plugging the above COUT3 expression into the Equation 1 we get

Equation 5. QgV(VDD-COM)_droop=COUT1B×COUT2×K23COUT1B+COUT2×K23+COUT2

The total decoupling capacitance close to the point of load (COUT_Total) is the summation of COUT1B, COUT2 and COUT3. The goal is to find a smallest COUT1B to reduce COUT_Total to the minimum for BOM cost and footprint saving, while retaining the desired load transient performance. The optimal COUT1B can be calculated by solving the partial derivative of COUT_Total equal to 0.

Equation 6. dCOUT_TotaldCOUT1B=ddCOUT1BCOUT1B+COUT2+COUT3=0
Including the above COUT3 and COUT2 expressions onto Equation 6, the optimal COUT1B is derived as

Equation 7. COUT1B=K23×Qg×K233+K232+K23+1+K232×K232+K23+1-1V(VDD-COM)_droop×K23+12×K232+K23+1

After that, solving Equation 5 including Equation 7, COUT2 can be solved as

Equation 8. COUT2=K23×Qg-1+K23×COUT1B×VVDD-COMdroop2×K23×V(VDD-COM)_droop+COUT1B2VVDD-COMdroop2K232+2K23+1+2COUT1BK23QgVVDD-COMdroop1-K23+K232Qg22×K23×V(VDD-COM)_droop
Overall, the design procedure of the three decoupling capacitors starts with COUT1B calculation, followed by COUT2 and then COUT3 calculation. The final capacitor values will be used to calculate RLIM, as described in the next section.