JAJSG66B November   2018  – March 2019 UCC21540 , UCC21541

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     機能ブロック図
  4. 改訂履歴
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety-Limiting Values
    9. 7.9  Electrical Characteristics
    10. 7.10 Switching Characteristics
    11. 7.11 Thermal Derating Curves
    12. 7.12 Typical Characteristics
  8. Parameter Measurement Information
    1. 8.1 Minimum Pulses
    2. 8.2 Propagation Delay and Pulse Width Distortion
    3. 8.3 Rising and Falling Time
    4. 8.4 Input and Disable Response Time
    5. 8.5 Programmable Dead Time
    6. 8.6 Power-up UVLO Delay to OUTPUT
    7. 8.7 CMTI Testing
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 9.3.2 Input and Output Logic Table
      3. 9.3.3 Input Stage
      4. 9.3.4 Output Stage
      5. 9.3.5 Diode Structure in the UCC2154x
    4. 9.4 Device Functional Modes
      1. 9.4.1 Disable Pin
      2. 9.4.2 Programmable Dead Time (DT) Pin
        1. 9.4.2.1 DT Pin Tied to VCCI
        2. 9.4.2.2 Connecting a Programming Resistor between DT and GND Pins
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Designing INA/INB Input Filter
        2. 10.2.2.2 Select Dead Time Resistor and Capacitor
        3. 10.2.2.3 Select External Bootstrap Diode and its Series Resistor
        4. 10.2.2.4 Gate Driver Output Resistor
        5. 10.2.2.5 Estimating Gate Driver Power Loss
        6. 10.2.2.6 Estimating Junction Temperature
        7. 10.2.2.7 Selecting VCCI, VDDA/B Capacitor
          1. 10.2.2.7.1 Selecting a VCCI Capacitor
          2. 10.2.2.7.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 10.2.2.7.3 Select a VDDB Capacitor
        8. 10.2.2.8 Application Circuits with Output Stage Negative Bias
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Component Placement Considerations
      2. 12.1.2 Grounding Considerations
      3. 12.1.3 High-Voltage Considerations
      4. 12.1.4 Thermal Considerations
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 開発サポート
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 関連リンク
    5. 13.5 コミュニティ・リソース
    6. 13.6 商標
    7. 13.7 静電気放電に関する注意事項
    8. 13.8 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • DWK|14
  • DW|16
サーマルパッド・メカニカル・データ
発注情報

Electrical Characteristics

VVCCI = 3.3 V or 5.0 V, 0.1-µF capacitor from VCCI to GND and 1-µF capacitor from VDDA/B to VSSA/B, VVDDA = VVDDB = 12 V, 1-µF capacitor from VDDA and VDDB to VSSA and VSSB, DT pin tied to VCCI, CL = 0 pF, TA = –40°C to +125°C unless otherwise noted(1)(2).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENTS
IVCCI VCCI quiescent current VINA = 0 V, VINB = 0 V 1.5 2.0 mA
IVDDA, IVDDB VDDA and VDDB quiescent current VINA = 0 V, VINB = 0 V 1.0 1.8 mA
IVCCI VCCI operating current current per channel (f = 500-kHz, 50% duty cycle) 2.5 mA
IVDDA, IVDDB VDDA and VDDB operating current current per channel (f = 500 kHz, 50% duty cycle), CL = 100 pF 2.5 mA
VCC SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS
VVCCI_ON UVLO Rising threshold 2.55 2.7 2.85 V
VVCCI_OFF UVLO Falling threshold 2.35 2.5 2.65 V
VVCCI_HYS UVLO Threshold hysteresis 0.2 V
VDD SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS
VVDDA_ON, VVDDB_ON UVLO Rising threshold 8 8.5 9 V
VVDDA_OFF, VVDDB_OFF UVLO Falling threshold 7.5 8 8.5 V
VVDDA_HYS, VVDDB_HYS UVLO Threshold hysteresis 0.5 V
INA, INB AND DISABLE
VINAH, VINBH, VDISH Input high threshold voltage 1.6 1.8 2 V
VINAL, VINBL, VDISL Input low threshold voltage 0.8 1 1.25 V
VINA_HYS, VINB_HYS, VDIS_HYS Input threshold hysteresis 0.8 V
OUTPUT
IOA+, IOB+ UCC21540
Peak output source current
CVDD = 10 µF, CLOAD = 0.18 µF, f = 1 kHz, bench measurement 2 4 A
UCC21541
Peak output source current
1 1.5
IOA-, IOB- UCC21540
Peak output sink current
3 6 A
UCC21541
Peak output sink current
1.5 2.5
ROHA, ROHB UCC21540, UCC21541
Output resistance at high state
IOUT = –10 mA, ROHA, ROHBdo not represent drive pull-up performance. See tRISE in Switching Characteristics and Output Stage for details. 5 10 Ω
ROLA, ROLB UCC21540 Output resistance at low state IOUT = 10 mA 0.55 1.1 Ω
UCC21541 Output resistance at low state 1.3 2.6
VOHA, VOHB Output voltage at high state VVDDA, VVDDB = 12 V, IOUT = –10 mA 11.9 11.95 V
VOLA, VOLB UCC21540 Output voltage at low state VVDDA, VVDDB = 12 V, IOUT = 10 mA 5.5 11 mV
UCC21541 Output voltage at low state 13 26
VOAPDA, VOAPDB Driver output (VOUTA, VOUTB) active pull down VVDDA and VVDDB unpowered, IOUTA, IOUTB = 200 mA 1.75 2.1 V
DEAD TIME AND OVERLAP PROGRAMMING
Dead time, DT DT pin tied to VCCI Overlap determined by INA, INB -
RDT = 10 kΩ 80 100 120 ns
RDT = 20 kΩ 160 200 240
RDT = 50 kΩ 400 500 600
Dead time matching, |DTAB-DTBA| RDT = 10 kΩ - 0 10 ns
RDT = 20 kΩ - 0 20
RDT = 50 kΩ - 0 65
Current direction in the testing conditions are defined to be positive into the pin and negative out of the specified terminal (unless otherwise noted).
Parameters with only a typical value are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's product warranty.