JAJSLR1A april   2022  – june 2023 UCC21717-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety Limiting Values
    8. 6.8  Electrical Characteristics
    9. 6.9  Switching Characteristics
    10. 6.10 Insulation Characteristics Curves
    11. 6.11 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Propagation Delay
      1. 7.1.1 Non-Inverting and Inverting Propagation Delay
    2. 7.2 Input Deglitch Filter
    3. 7.3 Active Miller Clamp
      1. 7.3.1 Internal Active Miller Clamp
    4. 7.4 Undervoltage Lockout (UVLO)
      1. 7.4.1 VCC UVLO
      2. 7.4.2 VDD UVLO
    5. 7.5 Overcurrent (OC) Protection
      1. 7.5.1 OC Protection with Soft Turn-OFF
    6. 7.6 Soft Turn-Off Triggered by RST/EN
      1. 7.6.1 Soft Turn-Off Triggered by RST/EN
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Power Supply
      2. 8.3.2  Driver Stage
      3. 8.3.3  VCC and VDD Undervoltage Lockout (UVLO)
      4. 8.3.4  Active Pulldown
      5. 8.3.5  Short Circuit Clamping
      6. 8.3.6  Internal Active Miller Clamp
      7. 8.3.7  Overcurrent and Short Circuit Protection
      8. 8.3.8  Soft Turn-Off
      9. 8.3.9  Fault (FLT), Reset and Enable (RST/EN)
      10. 8.3.10 Isolated Analog to PWM Signal Function
    4. 8.4 Device Functional Modes
  10. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Filters for IN+, IN-, and RST/EN
        2. 9.2.2.2 PWM Interlock of IN+ and IN-
        3. 9.2.2.3 FLT, RDY, and RST/EN Pin Circuitry
        4. 9.2.2.4 RST/EN Pin Control
        5. 9.2.2.5 Turn-On and Turn-Off Gate Resistors
        6. 9.2.2.6 Overcurrent and Short Circuit Protection
          1. 9.2.2.6.1 Protection Based on Power Modules with Integrated SenseFET
          2. 9.2.2.6.2 Protection Based on Desaturation Circuit
          3. 9.2.2.6.3 Protection Based on Shunt Resistor in Power Loop
        7. 9.2.2.7 Isolated Analog Signal Sensing
          1. 9.2.2.7.1 Isolated Temperature Sensing
          2. 9.2.2.7.2 Isolated DC Bus Voltage Sensing
        8. 9.2.2.8 Higher Output Current Using an External Current Buffer
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 サード・パーティ製品に関する免責事項
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 用語集
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-6D65BFC4-81D9-42A0-B61E-18621FCD30F0-low.gif Figure 5-1 UCC21717-Q1 DW Package SOIC 16 PinsTop View
Table 5-1 Pin Functions
PIN I/O(1) DESCRIPTION
NAME NO.
AIN 1 I Isolated analog sensing input, parallel a small capacitor to COM for better noise immunity. Tie to COM if unused.
OC 2 I Over current detection pin, support lower threshold for SenseFET, DESAT, and shunt resistor sensing. Tie to COM is unused.
COM 3 P Common ground reference, connecting to emitter pin for IGBT or source pin for SiC-MOSFET
OUTH 4 O Gate driver output pull up
VDD 5 P Positive supply rail for gate drive voltage, Bypassing a >10-μF capacitor to COM to support specified gate driver source peak current capability. Place decoupling capacitor close to the pin.
OUTL 6 O Gate driver output pull down
CLMPI 7 O Internal Active miller clamp, connecting this pin directly to the gate of the power transistor. Leave floating or tie to VEE if unused.
VEE 8 P Negative supply rail for gate drive voltage. Bypassing a >10-μF capacitor to COM to support specified gate driver sink peak current capability. Place decoupling capacitor close to the pin.
GND 9 P Input power supply and logic ground reference
IN+ 10 I Non-inverting gate driver control input. Tie to VCC if unused.
IN– 11 I Inverting gate driver control input. Tie to GND if unused.
RDY 12 O Power good for VCC-GND and VDD-COM. RDY is open drain configuration and can be paralleled with other RDY signals
FLT 13 O Active low fault alarm output upon over current or short circuit. FLT is in open drain configuration and can be paralleled with other faults
RST/EN 14 I The RST/EN serves two purposes:
1) Enable soft shutdown of the output side. The output is turned off by a soft turn off (STO) if EN is set to low;
2) Resets the OC condition signaled on FLT pin if terminal RST/EN is set to low for more than 1000ns. A reset of signal FLT is asserted at the rising edge of terminal RST/EN.
For automatic RESET function, this pin only serves as an EN pin. Enable / shutdown of the output side. The FET is turned off by a soft turn-off, if terminal EN is set to low.
VCC 15 P Input power supply from 3V to 5.5V, bypassing a >1-μF capacitor to GND. Place decoupling capacitor close to the pin.
APWM 16 O Isolated Analog Sensing PWM output. Leave floating if unused.
(1) P = Power, G = Ground, I = Input, O = Output