JAJSME3B March   2022  – January 2023 UCC21737-Q1

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety Limiting Values
    8. 6.8  Electrical Characteristics
    9. 6.9  Switching Characteristics
    10. 6.10 Insulation Characteristics Curves
    11. 6.11 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 Propagation Delay
      1. 7.1.1 Regular Turn-OFF
    2. 7.2 Input Deglitch Filter
    3. 7.3 Active Miller Clamp
      1. 7.3.1 External Active Miller Clamp
    4. 7.4 Undervoltage Lockout (UVLO)
      1. 7.4.1 VCC UVLO
      2. 7.4.2 VDD UVLO
      3. 7.4.3 VEE UVLO
    5. 7.5 Overcurrent (OC) Protection
      1. 7.5.1 OC Protection with Soft Turn-OFF
    6. 7.6 ASC Support
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Power Supply
      2. 8.3.2  Driver Stage
      3. 8.3.3  VCC, VDD, and VEE Undervoltage Lockout (UVLO)
      4. 8.3.4  Active Pulldown
      5. 8.3.5  Short Circuit Clamping
      6. 8.3.6  External Active Miller Clamp
      7. 8.3.7  Overcurrent and Short Circuit Protection
      8. 8.3.8  Soft Turn-off
      9. 8.3.9  Fault (FLT), Reset, and Enable (RST/EN)
      10. 8.3.10 ASC Support and APWM Monitor
    4. 8.4 Device Functional Modes
  9. Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Filters for IN+, IN-, and RST/EN
        2. 9.2.2.2 PWM Interlock of IN+ and IN-
        3. 9.2.2.3 FLT, RDY, and RST/EN Pin Circuitry
        4. 9.2.2.4 RST/EN Pin Control
        5. 9.2.2.5 Turnon and Turnoff Gate Resistors
        6. 9.2.2.6 External Active Miller Clamp
        7. 9.2.2.7 Overcurrent and Short Circuit Protection
          1. 9.2.2.7.1 Protection Based on Power Modules with Integrated SenseFET
          2. 9.2.2.7.2 Protection Based on Desaturation Circuit
          3. 9.2.2.7.3 Protection Based on Shunt Resistor in Power Loop
        8. 9.2.2.8 Higher Output Current Using an External Current Buffer
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 サード・パーティ製品に関する免責事項
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Typical Characteristics

VDD = 20 V, VEE = –5 V
Figure 6-4 Output High Drive Current vs Temperature
VDD = 20 V, VEE = –5 V
Figure 6-5 Output Low Driver Current vs Temperature
GUID-7571E427-948F-4FE3-8CD0-42E5D051ED20-low.gif
IN+ = High IN- = Low
Figure 6-6 IVCCQ Supply Current vs Temperature
GUID-696C5A1A-E547-4521-A433-16CB4A995A9C-low.gif
IN+ = Low IN- = Low
Figure 6-7 IVCCQ Supply Current vs Temperature
Figure 6-8 IVCCQ Supply Current vs Input Frequency
VDD = 20 V, VEE = –5 V IN+ = High, IN- = Low
Figure 6-9 IVDDQ Supply Current vs Temperature
VDD = 20 V, VEE = –5 V IN+ = Low, IN- = Low
Figure 6-10 IVDDQ Supply Current vs Temperature
VDD/VEE = 20 V/–5 V
Figure 6-11 IVDDQ Supply Current vs Input Frequency
GUID-5ADD3843-6A39-4F8E-8CFE-DB02C7EC4802-low.gifFigure 6-12 VCC UVLO vs Temperature
GUID-2F0A76A5-2ED2-4D6B-B033-8F3C27F86651-low.gifFigure 6-13 VDD UVLO vs Temperature
GUID-0CBBDEC8-513F-47A7-9645-63B5825B8552-low.gif
VCC = 3.3 V VDD = 18 V CL = 100 pF
RON = 0 Ω ROFF = 0 Ω
Figure 6-14 Propagation Delay tPDLH vs Temperature
GUID-70ED8074-EB56-4F7F-8A2E-C5D41A028654-low.gif
VCC = 3.3 V VDD = 18 V CL = 100 pF
RON = 0 Ω ROFF = 0 Ω
Figure 6-15 Propagation Delay tPDHL vs Temperature
GUID-88861CD9-7700-4A6B-A857-31CEC464E65E-low.gif
VCC = 3.3 V VDD = 18 V CL = 10 nF
RON = 0 Ω ROFF = 0 Ω
Figure 6-16 tr Rise Time vs Temperature
GUID-53AAFC66-83AE-4B76-AFD9-DC720C80FC58-low.gif
VCC = 3.3 V VDD = 18 V CL = 10 nF
RON = 0 Ω ROFF = 0 Ω
Figure 6-17 tf Fall Time vs Temperature
GUID-9FAAF859-0C98-4839-ACE0-D893182288B9-low.gifFigure 6-18 VOUTPD Output Active Pulldown Voltage vs Temperature
GUID-CEC412F4-98B4-478C-971A-F518084B87D1-low.gif
Figure 6-19 VCLP-OUT(H) Short Circuit Clamping Voltage vs Temperature
GUID-FAE6BBE5-6EC2-4608-8250-A68CC93CA905-low.gif
Figure 6-20 VCLP-OUT(L) Short Circuit Clamping Voltage vs Temperature
GUID-A554F9C0-198F-4160-9621-DFE13658A8CA-low.gifFigure 6-21 VCLMPTH Miller Clamp Threshold Voltage vs Temperature
GUID-1E535243-FFB2-4377-A10B-98883A92D80A-low.gif
Figure 6-22 ICLMPEL Miller Clamp Sink Current vs Temperature
GUID-8686F014-E949-4175-8D16-2B785DF019D8-low.gif
Figure 6-23 tDCLMPE Miller Clamp ON Delay Time vs Temperature
GUID-7D010CE8-94A1-4480-9AA1-51AAA7B3CC00-low.gif
Figure 6-24 VOCTH OC Detection Threshold vs Temperature