JAJSHR2B september   2019  – october 2020 UCC23511

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Function
    1.     Pin Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristics Curves
    12. 6.12 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Propagation Delay, rise time and fall time
    2. 7.2 IOH and IOL testing
    3. 7.3 CMTI Testing
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Supply
      2. 8.3.2 Input Stage
      3. 8.3.3 Output Stage
      4. 8.3.4 Protection Features
        1. 8.3.4.1 Undervoltage Lockout (UVLO)
        2. 8.3.4.2 Active Pulldown
        3. 8.3.4.3 Short-Circuit Clamping
    4. 8.4 Device Functional Modes
      1. 8.4.1 ESD Structure
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Selecting the Input Resistor
        2. 9.2.2.2 Gate Driver Output Resistor
        3. 9.2.2.3 Estimate Gate-Driver Power Loss
        4. 9.2.2.4 Estimating Junction Temperature
        5. 9.2.2.5 Selecting VCC Capacitor
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 PCB Material
    4. 11.4 Custom Design With WEBENCH® Tools
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DWY|6
サーマルパッド・メカニカル・データ
発注情報

11.2 Layout Example

Figure 11-1 shows a PCB layout example with the signals and key components labeled.

GUID-7187A420-7D54-41C0-9B9E-AADDC088AFFE-low.png
A. No PCB traces or copper are located between the primary and secondary side, which ensures isolation performance.
Figure 11-1 Layout Example

Figure 11-2 and Figure 11-3 show the top and bottom layer traces and copper.

GUID-215ED8F4-FAF0-41A1-B3B2-EC64C04F99B2-low.gifFigure 11-2 Top-Layer Traces and Copper
GUID-20945EE7-A312-4F87-8B25-A775156841CE-low.gifFigure 11-3 Bottom-Layer Traces and Copper (Flipped)

Figure 11-4 shows the 3D layout of the top view of the PCB.

GUID-D62C1BA7-0125-4B74-96F5-C19A05237D33-low.png
A. The location of the PCB cutout between primary side and secondary sides ensures isolation performance.
Figure 11-4 3-D PCB View