JAJSHD5D November   2010  – April  2019 UCD90160

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     簡略化されたアプリケーション回路図
  4. 改訂履歴
  5. 概要(続き)
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: I2C/SMBus/PMBus
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Rail Configuration
      2. 8.3.2 TI Fusion GUI
      3. 8.3.3 PMBus Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1  Power-Supply Sequencing
        1. 8.4.1.1 Turn-on Sequencing
        2. 8.4.1.2 Turn-off Sequencing
        3. 8.4.1.3 Sequencing Configuration Options
      2. 8.4.2  Pin-Selected Rail States
      3. 8.4.3  Voltage Monitoring
      4. 8.4.4  Fault Responses and Alert Processing
      5. 8.4.5  Shut Down All Rails and Sequence On (Resequence)
      6. 8.4.6  GPIOs
      7. 8.4.7  GPO Control
      8. 8.4.8  GPO Dependencies
        1. 8.4.8.1 GPO Delays
        2. 8.4.8.2 State Machine Mode Enable
      9. 8.4.9  GPI Special Functions
      10. 8.4.10 Power-Supply Enables
      11. 8.4.11 Cascading Multiple Devices
      12. 8.4.12 PWM Outputs
        1. 8.4.12.1 FPWM1-8
        2. 8.4.12.2 PWM1-4
      13. 8.4.13 Programmable Multiphase PWMs
      14. 8.4.14 Margining
        1. 8.4.14.1 Open-Loop Margining
        2. 8.4.14.2 Closed-Loop Margining
      15. 8.4.15 System Reset Signal
      16. 8.4.16 Watch Dog Timer
      17. 8.4.17 Run Time Clock
      18. 8.4.18 Data and Error Logging to Flash Memory
      19. 8.4.19 Brownout Function
      20. 8.4.20 PMBus Address Selection
    5. 8.5 Programming
      1. 8.5.1 Device Configuration and Programming
        1. 8.5.1.1 Full Configuration Update While in Normal Mode
      2. 8.5.2 JTAG Interface
      3. 8.5.3 Internal Fault Management and Memory Error Correction (ECC)
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
      4. 9.2.4 Estimating ADC Reporting Accuracy
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Overview

Electronic systems that include CPU, DSP, microcontroller, FPGA, ASIC, etc. can have multiple voltage rails and require certain power on/off sequences in order to function correctly. The UCD90160 can control up to 16 voltage rails and ensure correct power sequences during normal condition and fault conditions.

In addition to sequencing, UCD90160 can continuously monitor rail voltages, fault conditions, and report the system health information to a PMBus host, improving systems’ long term reliability.

Also, UCD90160 can protect electronic systems by responding to power system faults. The fault responses are conveniently configured by users through Fusion GUI. Fault events are stored in on-chip nonvolatile flash memory with time stamp in order to assist failure analysis.

System reliability can be improved through four-corner testing during system verification. During four-corner testing, each voltage rail is required to operate at the minimum and maximum output voltages, commonly known as margining. UCD90160 can perform closed-loop margining for up to 10 voltage rails. During normal operation, UCD90160 can also actively trim DC output voltages using the same margining circuitry.

UCD90160 supports both PMBus- and pin-based control environments. UCD90160 functions as a PMBus slave. It can communicate with PMBus host with PMBus commands, and control voltage rails accordingly. Also, UCD90160 can be controlled by up to 8 GPIO configured GPI pins. The GPIs can be used as Boolean logic input to control up to 16 Logic GPO outputs. Each Logic GPO has a flexible Boolean logic builder. Input signals of the Boolean logic builder can include GPIs, other Logic GPO outputs, and selectable system flags such as POWER_GOOD, faults, warnings, etc. A simple state machine is also available for each Logic GPO pin.

UCD90160 provides additional features such as pin-selected states, system watchdog, system reset, runtime clock, peak value log, reset counter, and so on. Pin-selected states feature allows users to use up to 3 GPIs to define up to 8 rail states. These states can implement system low-power modes as set out in the Advanced Configuration and Power Interface (ACPI) specification.