JAJSES0 February   2018 XTR305

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーション
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Voltage Output Mode
    6. 6.6  Electrical Characteristics: Current Output Mode
    7. 6.7  Electrical Characteristics: Operational Amplifier (OPA)
    8. 6.8  Electrical Characteristics: Instrumentation Amplifier (IA)
    9. 6.9  Electrical Characteristics: Current Monitor
    10. 6.10 Electrical Characteristics: Power and Digital
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Functional Features
      2. 7.3.2 Current Monitor
      3. 7.3.3 Error Flags
      4. 7.3.4 Power On/Off Glitch
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Voltage Output Mode
        2. 8.2.2.2  Current Output Mode
        3. 8.2.2.3  Input Signal Connection
        4. 8.2.2.4  Externally-Configured Mode: OPA and IA
        5. 8.2.2.5  Driver Output Disable
        6. 8.2.2.6  Driving Capacitive Loads and Loop Compensation
        7. 8.2.2.7  Internal Current Sources, Switching Noise, and Settling Time
        8. 8.2.2.8  IA Structure, Voltage Monitor
        9. 8.2.2.9  Digital I/O and Ground Considerations
        10. 8.2.2.10 Output Protection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 VQFN Package and Heat Sinking
    4. 10.4 Power Dissipation
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.3 VQFN Package and Heat Sinking

The XTR305 is available in a VQFN package. This leadless, near-chip-scale package maximizes board space and enhances thermal and electrical characteristics of the device through an exposed thermal pad.

Packages with an exposed thermal pad are specifically designed to provide excellent power dissipation, but printed circuit board (PCB) layout greatly influences overall heat dissipation. The thermal resistance from junction-to-ambient (θJA) is specified for the packages with the exposed thermal pad soldered to a normalized PCB, as described in the technical brief PowerPAD™ Thermally-Enhanced Package. See also EIA/JEDEC Specifications JESD51-0 to 7, VQFN/SON PCB Attachment, and Quad Flatpack No-Lead Logic Packages. These documents are available for download at www.ti.com.

NOTE

All thermal models have an accuracy variation of ±20%.

Component population, layout of traces, layers, and air flow strongly influence heat dissipation. Worst-case load conditions should be tested in the real environment to ensure proper thermal conditions. Minimize thermal stress for proper long-term operation with a junction temperature well below +125°C.

The exposed lead-frame die pad on the bottom of the package must be connected to the V− pin.