Address |
BITS |
Description |
Default |
R/W |
0x0020 |
(31:24) |
EVM_DIPSW(7:0)(1) |
Read from DLPLCRC910EVM |
R |
(23:7) |
Not used |
zeros |
R |
(6:4) |
DDC_VER(2:0)(2) |
Read from DLPC910 |
R |
(3:0) |
DMD_TYPE(3:0)(3) |
Read from DLPC910 |
R |
(1) EVM_DIPSW field is the 8-bit
value signaled to the Apps FPGA from the 8-position dip switch on the
DLPLCRC910EVM board. Out of box logic default is 0x03. See
DLPLCRC910EVM Dip Switch (SW2).
(2) DDC_VER field is the 3-bit value
signaled to the Apps FPGA at the DDC version input pins. The Apps FPGA does not
use this value.
(3) DMD_TYPE field is the 4-bit value
signaled to the Apps FPGA at the DMD type input pins. The Apps FPGA uses DMD
type to determine DMD resolution and clocks per row cycle. Additional
information is found in the
DLPC910 data
sheet.