DLPU125 june 2023
DLPC910 status-info signals are listed
in Table 3-5. The ddc_version, DMD_type,
and
DMD_irq
signals are from the DLPC910 controller. Only
DMD_type
is used by the Apps FPGA logic. The version and irq
signals are made available in status registers via the USB GPIF.
The DMD_speed_sel
signal is from a set of jumpers on the DLPLCRC910EVM board. The jumper settings are
used by DLPC910 controller and by Apps FPGA to determine clock frequency of the LVDS
high speed interface DLP9000X and DLP9000XUV.
Reference the DLPC910 data sheet for additional information.
Name | Apps FPGA I/O | Function |
---|---|---|
ddc_version(2:0) |
in | DLPC910 firmware version |
dmd_type(3:0) |
in | DLPC910 DMD type |
dmd_speed_sel(1:0) |
in | Apps/DLPC910 LVDS speed select jumpers |
dmd_irq |
in | DMD irq status signal |