JAJS124Q December   1999  – October 2019 UCC1895 , UCC2895 , UCC3895

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション概略図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1  ADS (Adaptive Delay Set)
      2. 7.3.2  CS (Current Sense)
      3. 7.3.3  CT (Oscillator Timing Capacitor)
      4. 7.3.4  DELAB and DELCD (Delay Programming Between Complementary Outputs)
      5. 7.3.5  EAOUT, EAP, and EAN (Error Amplifier)
      6. 7.3.6  OUTA, OUTB, OUTC, and OUTD (Output MOSFET Drivers)
      7. 7.3.7  PGND (Power Ground)
      8. 7.3.8  RAMP (Inverting Input of the PWM Comparator)
      9. 7.3.9  REF (Voltage Reference)
      10. 7.3.10 RT (Oscillator Timing Resistor)
      11. 7.3.11 GND (Analog Ground)
      12. 7.3.12 SS/DISB (Soft Start/Disable)
      13. 7.3.13 SYNC (Oscillator Synchronization)
      14. 7.3.14 VDD (Chip Supply)
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Programming DELAB, DELCD and the Adaptive Delay Set
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Power Loss Budget
        2. 8.2.2.2  Preliminary Transformer Calculations (T1)
        3. 8.2.2.3  QA, QB, QC, QD FET Selection
        4. 8.2.2.4  Selecting LS
        5. 8.2.2.5  Selecting Diodes DB and DC
        6. 8.2.2.6  Output Inductor Selection (LOUT)
        7. 8.2.2.7  Output Capacitance (COUT)
        8. 8.2.2.8  Select Rectifier Diodes
        9. 8.2.2.9  Input Capacitance (CIN)
        10. 8.2.2.10 Current Sense Network (CT, RCS, RR, DA)
          1. 8.2.2.10.1 Output Voltage Setpoint
          2. 8.2.2.10.2 Voltage Loop Compensation
          3. 8.2.2.10.3 Setting the Switching Frequency
          4. 8.2.2.10.4 Soft Start
          5. 8.2.2.10.5 Setting the Switching Delays
          6. 8.2.2.10.6 Setting the Slope Compensation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
      2. 11.1.2 関連リンク
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

8.2.1 Design Requirements

Table 1 lists the requirements for this application.

Table 1. UCC3895 Typical Application Design Requirements

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT CHARACTERISTICS
VIN DC input voltage range 370 390 410 V
IIN(max) Maximum input current VIN= 370 VDC to 410 VDC 2 A
OUTPUT CHARACTERISTICS
VOUT Output voltage VIN= 370 VDC to 410 VDC 11.4 12 12.6 V
IOUT Output current VIN= 370 VDC to 410 VDC 50 A
Output voltage transient 90% load step 600 mV
POUT Continuous output power VIN= 370 VDC to 410 VDC 600 W
Load regulation VIN = 370 VDC to 410 VDC, IOUT= 5 A to 50 A 140 mV
Line regulation VIN = 370 VDC to 410 VDC, IOUT= 5 A to 50 A 140 mV
Output ripple voltage VIN = 370 VDC to 410 VDC, IOUT= 5 A to 50 A 200 mV
SYSTEM
FSW Switching frequency 100 kHz
Full-load efficiency VIN= 370 VDC to 410 VDC, POUT= 500 W 92% 93%