JAJS365D January   2007  – October 2019 TPS2412 , TPS2413

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーションの図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Dissipation Ratings
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Definitions
      2. 9.3.2 TPS2412 vs TPS2413 – MOSFET Control Methods
      3. 9.3.3 N+1 Power Supply – Typical Connection
      4. 9.3.4 Input ORing – Typical Connection
      5. 9.3.5 System Design and Behavior With Transients
      6. 9.3.6 TPS2412 Regulation-Loop Stability
      7. 9.3.7 MOSFET Selection and R(RSET)
      8. 9.3.8 Gate Drive, Charge Pump and C(BYP)
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Recommended Operating Range
    2. 11.2 VDD, BYP, and Powering Options
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 関連リンク
    2. 13.2 コミュニティ・リソース
    3. 13.3 商標
    4. 13.4 静電気放電に関する注意事項
    5. 13.5 Glossary
  14. 14メカニカル、パッケージ、および注文情報

9.3.6 TPS2412 Regulation-Loop Stability

The TPS2412 uses an internal linear error amplifier to keep the external MOSFET from saturating at light load. This feature has the benefits of setting a turnoff above 0 V, providing a soft turnoff for slowly decaying input voltages, and helps droop-sharing redundancy at light load.

Although the control loop has been designed to accommodate a wide range of applications, there are a few guidelines to be followed to assure stability.

  • Select a MOSFET C(ISS) of 1 nF or greater
  • Use low ESR bulk capacitors on the output C terminal, typically greater than 100μF with less than 50 mΩ ESR
  • Maintain some minimum operational load (for example, 10 mA or more)

Symptoms of stability issues include V(AC) undershoot and possible fast turnoff on large-transient recovery, and a worst-case situation where the gate continually cycles on and off. These conditions are solved by following the previous rules. Loop stability should not be confused with tripping the fast comparator due to V(AC) tripping the gate off.

Although not common, a condition may arise where the DC-DC converter transient response may cause the GATE to cycle on and off at light load. The converter experiences a load spike when GATE transitions from OFF to ON because the ORed bus capacitor voltage charges abruptly by as much as a diode drop. The load spike may cause the supply output to droop and overshoot, which can result in the ORed capacitor peak charging to the overshoot voltage. When the supply output settles to its regulated value, the ORed bus may be higher than the source, causing the TPS2412/13 to turn the GATE off. While this may not actually cause a problem, its occurrence may be mitigated by control of the power supply transient characteristic and increasing its output capacitance while increasing the ORed load to capacitance ratio. Adjusting the TPS2412/13 turnoff threshold to desensitize the redundant ORing device may help as well. Careful attention to layout and charge-pump noise around the TPS2412/13 helps with noise margin.

The linear gate driver has a pullup current of 290 μA and pulldown current of 3 mA typical.