JAJSCT8D March   2015  – March 2017 LMG5200

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
  4. 改訂履歴
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 Propagation Delay and Mismatch Measurement
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Control Inputs
      2. 8.3.2 Start-up and UVLO
      3. 8.3.3 Bootstrap Supply Voltage Clamping
      4. 8.3.4 Level Shift
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 VCC Bypass Capacitor
        2. 9.2.2.2 Bootstrap Capacitor
        3. 9.2.2.3 Power Dissipation
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報
    1. 13.1 パッケージ情報

Detailed Description

Overview

Figure 10 shows the LMG5200, half-bridge, GaN power stage with highly integrated high-side and low-side gate drivers, which includes built-in UVLO protection circuitry and an overvoltage clamp circuitry. The clamp circuitry limits the bootstrap refresh operation to ensure that the high-side gate driver overdrive does not exceed 5.4 V. The device integrates two, 15-mΩ GaN FETs in a half-bridge configuration. The device can be used in many isolated and non-isolated topologies allowing very simple integration. The package is designed to minimize the loop inductance while keeping the PCB design simple. The drive strengths for turnon and turnoff are optimized to ensure high voltage slew rates without causing any excessive ringing on the gate or power loop.

Functional Block Diagram

Figure 10 shows the functional block diagram of the LMG5200 device with integrated high-side and low-side GaN FETs.

LMG5200 fbd_snoscy4.gif
Figure 10. Functional Block Diagram

Feature Description

The LMG5200 device brings ease of designing high power density boards without the need for underfill while maintaining creepage and clearance requirements. The propagation delays between the high-side gate driver and low-side gate driver are matched to allow very tight control of dead time. Controlling the dead time is critical in GaN-based applications to maintain high efficiency. HI and LI can be independently controlled to minimize the third quadrant conduction of the low-side FET for hard switched buck converters. A very small propagation mismatch between the HI and LI to the drivers for both the falling and rising thresholds ensures dead times of < 10 ns. Co-packaging the GaN FET half-bridge with the driver ensures minimized common source inductance. This minimized inductance has a significant performance impact on hard-switched topologies.

The built-in bootstrap circuit with clamp prevents the high-side gate drive from exceeding the GaN FETs maximum gate-to-source voltage (Vgs) without any additional external circuitry. The built-in driver has an undervoltage lockout (UVLO) on the VDD and bootstrap (HB-HS) rails. When the voltage is below the UVLO threshold voltage, the device ignores both the HI and LI signals to prevent the GaN FETs from being partially turned on. Below UVLO, if there is sufficient voltage (VVCC > 2.5 V), the driver actively pulls the high-side and low-side gate driver output low. The UVLO threshold hysteresis of 200 mV prevents chattering and unwanted turnon due to voltage spikes. Use an external VCC bypass capacitor with a value of 0.1 µF or higher. TI recommends a size of 0402 to minimize trace length to the pin. Place the bypass and bootstrap capacitors as close as possible to the device to minimize parasitic inductance.

Control Inputs

The LMG5200's inputs pins are independently controlled with TTL input thresholds and can withstand voltages up to 12V regardless of the VDD voltage. This allows the inputs to be directly connected to the outputs of an analog PWM controller with up to 12V power supply, eliminating the need for a buffer stage.

In order to allow flexibility to optimize deadtime according to design needs, the LMG5200 does not implement an overlap protection functionality. If both HI and LI are asserted, both the high-side and low-side GaN FETs are turned on. Careful consideration must be applied to the control inputs in order to avoid a shoot-through condition.

Start-up and UVLO

The LMG5200 has an UVLO on both the VCC and HB (bootstrap) supplies. When the VCC voltage is below the threshold voltage of 3.8 V, both the HI and LI inputs are ignored, to prevent the GaN FETs from being partially turned on. Also, if there is insufficient VCC voltage, the UVLO actively pulls the high- and low-side GaN FET gates low. When the HB to HS bootstrap voltage is below the UVLO threshold of 3.2 V, only the high-side GaN FET gate is pulled low. Both UVLO threshold voltages have 200 mV of hysteresis to avoid chattering.

Table 1. VCC UVLO Feature Logic Operation

CONDITION (VHB-HS > VHBR for all cases below) HI LI SW
VCC - VSS < VCCR during device start-up H L Hi-Z
VCC - VSS < VCCR during device start-up L H Hi-Z
VCC - VSS < VCCR during device start-up H H Hi-Z
VCC - VSS < VCCR during device start-up L L Hi-Z
VCC - VSS < VCCR - VCC(hyst) after device start-up H L Hi-Z
VCC - VSS < VCCR - VCC(hyst) after device start-up L H Hi-Z
VCC - VSS < VCCR - VCC(hyst) after device start-up H H Hi-Z
VCC - VSS < VCCR - VCC(hyst) after device start-up L L Hi-Z

Table 2. VHB-HS UVLO Feature Logic Operation

CONDITION (VCC > VCCR for all cases below) HI LI SW
VHB-HS < VHBR during device start-up H L Hi-Z
VHB-HS < VHBR during device start-up L H PGND
VHB-HS < VHBR during device start-up H H PGND
VHB-HS < VHBR during device start-up L L Hi-Z
VHB-HS < VHBR - VHB(hyst) after device start-up H L Hi-Z
VHB-HS < VHBR - VHB(hyst) after device start-up L H PGND
VHB-HS < VHBR - VHB(hyst) after device start-up H H PGND
VHB-HS < VHBR - VHB(hyst) after device start-up L L Hi-Z

Bootstrap Supply Voltage Clamping

The high-side bias voltage is generated using a bootstrap technique and is internally clamped at 5 V (typical). This clamp prevents the gate voltage from exceeding the maximum gate-source voltage rating of the enhancement-mode GaN FETs.

Level Shift

The level-shift circuit is the interface from the high-side input HI to the high-side driver stage, which is referenced to the switch node (HS). The level shift allows control of the high-side GaN FET gate driver output, which is referenced to the HS pin and provides excellent delay matching with the low-side driver.

Device Functional Modes

The LMG5200 operates in normal mode and UVLO mode. See Start-up and UVLO for information on UVLO operation mode. In the normal mode, the output state is dependent on the states of the HI and LI pins. Table 3 lists the output states for different input pin combinations. Note that when both HI and LI are asserted, both GaN FETs in the power stage are turned on. Careful consideration must be applied to the control inputs in order to avoid this state, as it will result in a shoot-through condition, which can permanently damage the device.

Table 3. Truth Table

HI LI HIGH-SIDE GaN FET LOW-SIDE GaN FET SW
L L OFF OFF Hi-Z
L H OFF ON PGND
H L ON OFF VIN
H H ON ON - - -