JAJSDJ8A April   2017  – October 2021 ADC12D1620QML-SP

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Converter Electrical Characteristics: Static Converter Characteristics
    6. 6.6  Converter Electrical Characteristics: Dynamic Converter Characteristics
    7. 6.7  Converter Electrical Characteristics: Analog Input/Output and Reference Characteristics
    8. 6.8  Converter Electrical Characteristic: Channel-to-Channel Characteristics
    9. 6.9  Converter Electrical Characteristics: LVDS CLK Input Characteristics
    10. 6.10 Electrical Characteristics: AutoSync Feature
    11. 6.11 Converter Electrical Characteristics: Digital Control and Output Pin Characteristics
    12. 6.12 Converter Electrical Characteristics: Power Supply Characteristics
    13. 6.13 Converter Electrical Characteristics: AC Electrical Characteristics
    14. 6.14 Electrical Characteristics: Delta Parameters
    15. 6.15 Timing Requirements: Serial Port Interface
    16. 6.16 Timing Requirements: Calibration
    17. 6.17 Quality Conformance Inspection
    18. 6.18 Timing Diagrams
    19. 6.19 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Operation Summary
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Control and Adjust
        1. 7.3.1.1 AC- and DC-Coupled Modes
        2. 7.3.1.2 Input Full-Scale Range Adjust
        3. 7.3.1.3 Input Offset Adjust
        4. 7.3.1.4 Low-Sampling Power-Saving Mode (LSPSM)
        5. 7.3.1.5 DES Timing Adjust
        6. 7.3.1.6 Sampling Clock Phase Adjust
      2. 7.3.2 Output Control and Adjust
        1. 7.3.2.1 SDR / DDR Clock
        2. 7.3.2.2 LVDS Output Differential Voltage
        3. 7.3.2.3 LVDS Output Common-Mode Voltage
        4. 7.3.2.4 Output Formatting
        5. 7.3.2.5 Test-Pattern Mode
        6. 7.3.2.6 Time Stamp
      3. 7.3.3 Calibration Feature
        1. 7.3.3.1 Calibration Control Pins and Bits
        2. 7.3.3.2 How to Execute a Calibration
        3. 7.3.3.3 On-Command Calibration
        4. 7.3.3.4 Calibration Adjust
          1. 7.3.3.4.1 Read/Write Calibration Settings
        5. 7.3.3.5 Calibration and Power-Down
        6. 7.3.3.6 Calibration and the Digital Outputs
      4. 7.3.4 Power Down
      5. 7.3.5 Low-Sampling Power-Saving Mode (LSPSM)
    4. 7.4 Device Functional Modes
      1. 7.4.1 DES/Non-DES Mode
      2. 7.4.2 Demux/Non-Demux Mode
    5. 7.5 Programming
      1. 7.5.1 Control Modes
        1. 7.5.1.1 Non-ECM
          1. 7.5.1.1.1  Dual-Edge Sampling Pin (DES)
          2. 7.5.1.1.2  Non-Demultiplexed Mode Pin (NDM)
          3. 7.5.1.1.3  Dual Data-Rate Phase Pin (DDRPh)
          4. 7.5.1.1.4  Calibration Pin (CAL)
          5. 7.5.1.1.5  Low-Sampling Power-Saving Mode Pin (LSPSM)
          6. 7.5.1.1.6  Power-Down I-Channel Pin (PDI)
          7. 7.5.1.1.7  Power-Down Q-Channel Pin (PDQ)
          8. 7.5.1.1.8  Test-Pattern Mode Pin (TPM)
          9. 7.5.1.1.9  Full-Scale Input-Range Pin (FSR)
          10. 7.5.1.1.10 AC- or DC-Coupled Mode Pin (VCMO)
          11. 7.5.1.1.11 LVDS Output Common-Mode Pin (VBG)
        2. 7.5.1.2 Extended Control Mode
          1. 7.5.1.2.1 Serial Interface
    6. 7.6 Register Maps
      1. 7.6.1 Register Definitions
  8. Application Information Disclaimer
    1. 8.1 Application Information
      1. 8.1.1 Analog Inputs
        1. 8.1.1.1 Acquiring the Input
        2. 8.1.1.2 Driving the ADC in DES Mode
        3. 8.1.1.3 FSR and the Reference Voltage
        4. 8.1.1.4 Out-Of-Range Indication
        5. 8.1.1.5 AC-Coupled Input Signals
        6. 8.1.1.6 DC-Coupled Input Signals
        7. 8.1.1.7 Single-Ended Input Signals
      2. 8.1.2 Clock Inputs
        1. 8.1.2.1 CLK Coupling
        2. 8.1.2.2 CLK Frequency
        3. 8.1.2.3 CLK Level
        4. 8.1.2.4 CLK Duty Cycle
        5. 8.1.2.5 CLK Jitter
        6. 8.1.2.6 CLK Layout
      3. 8.1.3 LVDS Outputs
        1. 8.1.3.1 Common-Mode and Differential Voltage
        2. 8.1.3.2 Output Data Rate
        3. 8.1.3.3 Terminating Unused LVDS Output Pins
      4. 8.1.4 Synchronizing Multiple ADC12D1620 Devices in a System
        1. 8.1.4.1 AutoSync Feature
        2. 8.1.4.2 DCLK Reset Feature
      5. 8.1.5 Temperature Sensor
    2. 8.2 Radiation Environments
      1. 8.2.1 Total Ionizing Dose
      2. 8.2.2 Single Event Latch-Up and Functional Interrupt
      3. 8.2.3 Single Event Upset
    3. 8.3 Cold Sparing
  9. Power Supply Recommendations
    1. 9.1 System Power-On Considerations
      1. 9.1.1 Control Pins
      2. 9.1.2 Power On in Non-ECM
      3. 9.1.3 Power On in ECM
      4. 9.1.4 Power-on and Data Clock (DCLK)
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Power Planes
      2. 10.1.2 Bypass Capacitors
      3. 10.1.3 Ground Planes
      4. 10.1.4 Power System Example
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
    4. 10.4 Board Mounting Recommendation
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Third-Party Products Disclaimer
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Engineering Samples

Converter Electrical Characteristics: AC Electrical Characteristics

The following specifications apply after calibration for VA = VDR = VTC = VE = 1.9 V; I and Q channels AC-coupled, FSR pin = high; CL = 10 pF; differential AC-coupled sine wave input clock, fCLK = 1.6 GHz at 0.5 VP-P with 50% duty cycle; VBG = floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2 demultiplex non-DES mode; I and Q channels; duty-cycle stabilizer on.(1)(2)
PARAMETERCONDITIONSSUB-GROUPSMINTYP(3)MAXUNIT
INPUT CLOCK (CLK)
fCLK (max)Maximum input clock frequencyNon-LSPSM[9, 10, 11]1.6GHz
LSPSM[9, 10, 11]800MHz
fCLK (min)Minimum input clock frequencyNon-LSPSMNon-DES mode; LFS = 1b[9, 10, 11]200MHz
DES mode250
LSPSMNon-DES mode[9, 10, 11]200MHz
Input clock duty cycle(4)fCLK(min) ≤ fCLK ≤ fCLK (max)20%50%80%
tCLInput clock low time(4)200500ps
tCHInput clock high time(4)200500ps
DCLK_RST
tSRSetup time DCLK_RST±45ps
tHRHold time DCLK_RST±45ps
tPWRPulse width DCLK_RST±5Input Clock Cycles
DATA CLOCK (DCLKI, DCLKQ)
DCLK duty cycle50%
tSYNC_DLYDCLK synchronization delay90° mode4Input Clock Cycles
0° mode5
tLHTDifferential low-to-high transition time10% to 90%, CL = 2.5-pF200ps
tHLTDifferential high-to-low transition time10% to 90%, CL = 2.5-pF200ps
tSUData-to-DCLK set-up timeDDR mode, 90° DCLK500ps
tHDCLK-to-data hold timeDDR mode, 90° DCLK500ps
tOSKDCLK-to-data output skew50% of DCLK transition to 50% of data transition±50ps
DATA INPUT-TO-OUTPUT
tADSampling (aperture) delayInput CLK+ rise to acquisition of data1.3ns
tAJAperture jitter0.2ps (rms)
tODInput clock-to data output delay (in addition to tLAT)50% of input clock transition to 50% of data transition3.2ns
tLATLatency in
1:2 demux non-DES mode(4)
DI, DQ outputs[4, 5, 6]34Input Clock Cycles
DId, DQd outputs[4, 5, 6]35
Latency in
1:4 demux DES mode(4)
DI outputs[4, 5, 6]34Input Clock Cycles
DQ outputs[4, 5, 6]34.5
DId outputs[4, 5, 6]35
DQd outputs[4, 5, 6]35.5
Latency in
non-demux non-DES mode(4)
DI outputs[4, 5, 6]34Input Clock Cycles
DQ outputs[4, 5, 6]34
Latency in
non-demux DES mode(4)
DI outputs[4, 5, 6]34Input Clock Cycles
DQ outputs[4, 5, 6]34.5
tORROver range recovery timeDifferential VIN step from ±1.2 V to 0 V to get accurate conversion1Input Clock Cycle
tWUPD low-to-rated accuracy conversion (wake-up time)Non-DES mode500ns
DES mode1µs
The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device.
GUID-0E180FB8-5707-431A-A0F2-8F15E7197F19-low.gif
The maximum clock frequency for non-demux mode is 1 GHz.
Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average outgoing quality level (AOQL).
This parameter is specified by design and/or characterization and is not tested in production.