JAJSF66B april   2018  – february 2023 TPS62147 , TPS62148

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Schematic
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Precise Enable
      2. 9.3.2 Power Good (PG)
      3. 9.3.3 MODE
      4. 9.3.4 Undervoltage Lockout (UVLO)
      5. 9.3.5 Thermal Shutdown
    4. 9.4 Device Functional Modes
      1. 9.4.1 Pulse Width Modulation (PWM) Operation
      2. 9.4.2 Power Save Mode Operation (PWM/PFM)
      3. 9.4.3 100% Duty-Cycle Operation
      4. 9.4.4 Current Limit And Short Circuit Protection (for TPS62148)
      5. 9.4.5 HICCUP Current Limit And Short Circuit Protection (for TPS62147)
      6. 9.4.6 Soft Start / Tracking (SS/TR)
      7. 9.4.7 Output Discharge Function (TPS62148 only)
      8. 9.4.8 Starting into a Pre-Biased Load
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Programming the Output Voltage
      2. 10.1.2 External Component Selection
      3. 10.1.3 Inductor Selection
      4. 10.1.4 Capacitor Selection
        1. 10.1.4.1 Output Capacitor
        2. 10.1.4.2 Input Capacitor
        3. 10.1.4.3 Soft-Start Capacitor
      5. 10.1.5 Tracking Function
      6. 10.1.6 Output Filter and Loop Stability
    2. 10.2 Typical Applications
      1. 10.2.1 Typical Application with Adjustable Output Voltage
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
    3. 10.3 System Examples
      1. 10.3.1 LED Power Supply
      2. 10.3.2 Powering Multiple Loads
      3. 10.3.3 Voltage Tracking
      4. 10.3.4 Precise Soft-Start Timing
    4. 10.4 Power Supply Recommendations
    5. 10.5 Layout
      1. 10.5.1 Layout Guidelines
      2. 10.5.2 Layout Example
      3. 10.5.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 サード・パーティ製品に関する免責事項
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  12. 12Mechanical, Packaging, and Orderable Information

9.4.3 100% Duty-Cycle Operation

The duty cycle of the buck converter is given by D = VOUT / VIN and increases as the input voltage comes close to the output voltage. The minimum off-time is about 80 ns. When the minimum off-time is reached, TPS62147, TPS62148 scale down the switching frequency while they approach 100% mode. In 100% mode the high-side switch is on continuously. The high-side switch stays turned on as long as the output voltage is below the internal set point. This allows the conversion of small input to output voltage differences, for example for longest operation time of battery-powered applications. In 100% duty-cycle mode, the low-side FET is switched off.

The minimum input voltage to maintain output voltage regulation, depending on the load current and the output voltage level, can be calculated as:

Equation 7. GUID-3C70D4E3-844C-4FD6-8D05-B44B79F589C9-low.gif

where

  • IOUT is the output current,
  • RDS(on) is the on-state resistance of the high-side FET and
  • RL is the dc resistance of the inductor used.