JAJSFM3E February   2015  – June 2018 LMH1218

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      SPI概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Descriptions – SPI Mode/ Mode_SEL = 1 kΩ to VDD
    2.     Pin Descriptions – SMBUS Mode/ MODE_SEL = 1 kΩ to GND
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Recommended SMBus Interface AC Timing Specifications
    7. 7.7 Serial Parallel Interface (SPI) Bus Interface AC Timing Specifications
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Loss of Signal Detector
      2. 8.3.2 Continuous Time Linear Equalizer (CTLE)
      3. 8.3.3 2:1 Multiplexer
      4. 8.3.4 Clock and Data Recovery
      5. 8.3.5 Eye Opening Monitor (EOM)
      6. 8.3.6 Fast EOM
        1. 8.3.6.1 SMBus Fast EOM Operation
        2. 8.3.6.2 SPI Fast EOM Operation
      7. 8.3.7 LMH1218 Device Configuration
        1. 8.3.7.1 MODE_SEL
        2. 8.3.7.2 ENABLE
        3. 8.3.7.3 LOS_INT_N
        4. 8.3.7.4 LOCK
        5. 8.3.7.5 SMBus MODE
        6. 8.3.7.6 SMBus READ/WRITE Transaction
        7. 8.3.7.7 SPI Mode
          1. 8.3.7.7.1 SPI READ/WRITE Transaction
          2. 8.3.7.7.2 SPI Write Transaction Format
          3. 8.3.7.7.3 SPI Read Transaction Format
        8. 8.3.7.8 SPI Daisy Chain
          1. 8.3.7.8.1 SPI Daisy Chain Write Example
          2. 8.3.7.8.2 SPI Daisy Chain Write Read Example
            1. 8.3.7.8.2.1 SPI Daisy Chain Length of Daisy Chain Illustration
      8. 8.3.8 Power-On Reset
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 Global Registers
      2. 8.6.2 Receiver Registers
      3. 8.6.3 CDR Registers
      4. 8.6.4 Transmitter Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 General Guidance for All Applications
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
    4. 9.4 Initialization Set Up
      1. 9.4.1 Selective Data Rate Lock
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Solder Profile
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

8.6.1 Global Registers

Table 5. Global Registers

REGISTER NAME BITS FIELD REGISTER ADDRESS DEFAULT R/RW DESCRIPTION
SMBus Observation Reg_0x00 Share 0x00 SMBus Address Observation
7 SMBUS_addr3 0 R SMBus strap observation
6 SMBUS_addr2 0 R
5 SMBUS_addr1 0 R
4 SMBUS_addr0 0 R
3 Reserved 0 RW
2 Reserved 0 RW
1 Reserved 0 RW
0 Reserved 0 RW
Reset Shared Regs Reg 0x04 Share 0x01 Shared Register Reset
7 Reserved 0 RW
6 rst_i2c_regs 0 RW 1: Reset Shared Registers
0: Normal operation
5 Reserved 0 RW
4 Reserved 0 RW
3 Reserved 0 RW
2 Reserved 0 RW
1 Reserved 0 RW
0 Reserved 1 RW
Enable SMBus Strap Reg 0x06 Share 0x00 Allow SMBus strap observation
7 Reserved 0 RW
6 Reserved 0 RW
5 Reserved 0 RW
4 Reserved 0 RW
3 Test control[3] 0 RW Set to >9 to allow strap observation on share reg 0x00
2 Test control[2] 0 RW
1 Test control[1] 0 RW
0 Test control[0] 0 RW
Device Version Reg 0xF0 Share 0x01 Device Version
7 VERSION[7] 0 RW Device revision
6 VERSION[6] 0 RW
5 VERSION[5] 0 RW
4 VERSION[4] 0 RW
3 VERSION[3] 0 RW
2 VERSION[2] 0 RW
1 VERSION[1] 0 RW
0 VERSION[0] 1 RW
Device ID Reg 0xF1 Share 0x60 Device ID
7 DEVICE_ID[7] 0 RW Device ID
6 DEVICE_ID[6] 1 RW
5 DEVICE_ID[5] 1 RW
4 DEVICE_ID[4] 0 RW
3 DEVICE_ID[3] 0 RW
2 DEVICE_ID[2] 0 RW
1 DEVICE_ID[1] 0 RW
0 DEVICE_ID[0] 0 RW
Channel Control Reg 0xFF Control 0x00 Enable Channel Control
7 Reserved 0 RW
6 Reserved 0 RW
5 los_int_bus_sel 0 RW 1: Selects interrupt onto LOS pin
0: Select signal detect onto LOS pin
4 Reserved 0 RW
3 Reserved 0 RW
2 en_ch_Access 0 RW 1: Enables access to channel registers
0: Enable access to share register
1 Reserved 0 RW
0 Reserved 0 RW
Reset_Channel_Regs Reg_0x00 Channel 0x00 Reset all Channel Registers to Default Values
7 Reserved 0
6 Reserved 0
5 Reserved 0
4 Reserved 0
3 Reserved 0
2 Rst_regs 0 1: Reset Channel Registers ( self clearing )
0: Normal operation
1 Reserved 0
0 Reserved 0
LOS_status Reg_0x01 Channel 0x00 Signal Detect Status
7 Reserved 0 RW
6 Reserved 0 RW
5 Reserved 0 RW
4 Reserved 0 RW
3 Reserved 0 RW
2 Reserved 0 RW
1 LOS1 0 R 1: Loss of signal on IN1
0: Signal present on IN1
0 LOS0 0 R 1: Loss of signal on IN0
0: Signal present on IN0
CDR_Status_1 Reg_0x02 Channel 0x00 CDR Status
7 Reserved 0 R
6 Reserved 0 R
5 Reserved 0 R
4 cdr_status[4] 0 R 11: CDR locked
00: CDR not locked
3 cdr_status[3] 0 R
2 Reserved 0 R
1 Reserved 0 R
0 Reserved 0 R
Interrupt Status Register Reg 0x54 Channel 0x00 Interrupt Status ( clears upon read )
7 Sigdet 0 R 1: Signal Detect from the selected input asserted
0: Signal Detect from the selected input de-asserted
6 cdr_lock_int 0 R 1: CDR Lock interrupt
0: No interrupt from CDR Lock
5 signal_det1_int 0 R 1: IN1 Signal Detect interrupt
0: No interrupt from IN1 Signal Detect
4 signal_det0_int 0 R 1: IN0 Signal Detect interrupt
0: No interrupt from IN0 Signal Detect
3 heo_veo_int 0 R 1: HEO_VEO Threshold reached interrupt
0: No interrupt from HEO_VEO
2 cdr_lock_loss_int 0 R 1: CDR loss of lock interrupt
0: No interrupt from CDR lock
1 signal_det1_loss_int 0 R 1: IN1 Signal Detect loss interrupt
0: No interrupt from IN1 Signal Detect
0 signal_det0_loss_int 0 R 1: IN0 Signal Detect loss interrupt
0: No interrupt from IN0 Signal Detect
Interrupt Control Reg 0x56 Channel 0x00 Interrupt Mask
7 Reserved 0 RW
6 cdr_lock_int_en 0 RW 1: Enable Interrupt if CDR lock is achieved
0: Disable interrupt if CDR lock is achieved
5 signal_det1_int_en 0 RW 1: Enable interrupt if IN1 Signal Detect is asserted
0: Disable interrupt if IN1 Signal Detect is asserted
4 signal_det0_int_en 0 RW 1: Enable interrupt if IN0 Signal Detect is asserted
0: Disable interrupt if IN0 Signal Detect is asserted
3 heo_veo_int_en 0 RW 1: Enable interrupt if HEO-VEO threshold is reached
0: Disable interrupt due to HEO-VEO threshold
2 cdr_lock_loss_int_en 0 RW 1: Enable interrupt if CDR loses lock
0: Disable interrupt if CDR loses lock
1 signal_det1_loss_int_en 0 RW 1: Enable interrupt if there is loss of signal on IN1
0: Disable interrupt if there is loss of signal on IN1
0 signal_det0_loss_int_en 0 RW 1: Enable interrupt if there is loss of signal on IN0
0: Disable interrupt if there is loss of signal on IN0