JAJSG97A September   2018  – March 2019 LMG3410R050 , LMG3411R050

ADVANCE INFORMATION for pre-production products; subject to change without notice.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      ブロック概略図
      2.      100V/nsを超えるスイッチング性能
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
  7. Parameter Measurement Information
    1. 7.1 Switching Parameters
      1. 7.1.1 Turn-on Delays
      2. 7.1.2 Turn-off Delays
      3. 7.1.3 Drain Slew Rate
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Direct-Drive GaN Architecture
      2. 8.3.2 Internal Buck-Boost DC-DC Converter
      3. 8.3.3 Internal Auxiliary LDO
      4. 8.3.4 Fault Detection
        1. 8.3.4.1 Over-current Protection
        2. 8.3.4.2 Over-Temperature Protection and UVLO
      5. 8.3.5 Drive Strength Adjustment
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low-Power Mode
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Slew Rate Selection
          1. 9.2.2.1.1 Startup and Slew Rate with Bootstrap High-Side Supply
        2. 9.2.2.2 Signal Level-Shifting
        3. 9.2.2.3 Buck-Boost Converter Design
      3. 9.2.3 Application Curves
    3. 9.3 Paralleling GaN Devices
    4. 9.4 Do's and Don'ts
  10. 10Power Supply Recommendations
    1. 10.1 Using an Isolated Power Supply
    2. 10.2 Using a Bootstrap Diode
      1. 10.2.1 Diode Selection
      2. 10.2.2 Managing the Bootstrap Voltage
      3. 10.2.3 Reliable Bootstrap Start-up
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Power Loop Inductance
      2. 11.1.2 Signal Ground Connection
      3. 11.1.3 Bypass Capacitors
      4. 11.1.4 Switch-Node Capacitance
      5. 11.1.5 Signal Integrity
      6. 11.1.6 High-Voltage Spacing
      7. 11.1.7 Thermal Recommendations
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

Overview

LMG341xR050 is a high-performance 600-V GaN transistor with integrated gate driver. The GaN transistor provides ultra-low input and output capacitance and zero reverse recovery. The lack of reverse recovery enables efficient operation in half-bridge and bridge-based topologies.

TI utilizes a Direct Drive architecture to control the GaN FET within the LMG341xR050. When the driver is powered up, the GaN FET is controlled directly with the integrated gate driver. This architecture provides superior switching performance compared with the traditional cascode approach.

The integrated driver solves a number of challenges using GaN devices. The LMG341xR050 contains a driver specifically tuned to the GaN device for fast driving without ringing on the gate. The driver ensures the device stays off for high drain slew rates up to 150 V/ns. In addition, the integrated driver protects against faults by providing overcurrent and overtemperature protection. This feature can protect the system in case of a device failure, or prevent a device failure in the case of a controller error or malfunction. LMG3410R050 and LMG3411R050 have the same design and features, except the handling of OCP events. LMG3410R050 adopts a latch-off strategy at OCP events, while LMG3411R050 can realize cycle-by-cycle current limit function. Please refer to Fault Detection for more details.

Unlike silicon MOSFETs, there is no p-n junction from source to drain in GaN devices. That is why GaN devices have no reverse recovery losses. However, the GaN device can still conduct from source to drain in 3rd quadrant of operation similar to a body diode but with higher voltage drop and higher conduction loss. 3rd quadrant operation can be defined as follows; when the GaN device is turned off and negative current pulls the drain node voltage to be lower than its source. The voltage drop across GaN device during 3rd quadrant operation is high; therefore, it is recommended to operate with synchronous switching and keep the duration of 3rd quadrant operation at minimum.