JAJSGG5D November   2018  – March 2021 TPS3703-Q1

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD
      2. 8.3.2 SENSE
      3. 8.3.3 RESET
      4. 8.3.4 Capacitor Time (CT)
      5. 8.3.5 Manual Reset ( MR)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > VDD(MIN))
      2. 8.4.2 Undervoltage Lockout (VPOR < VDD < UVLO)
      3. 8.4.3 Power-On Reset (VDD < VPOR)
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Voltage Threshold Accuracy
      2. 9.1.2 CT Reset Time Delay
        1. 9.1.2.1 Factory-Programmed Reset Delay Timing
        2. 9.1.2.2 Programmable Reset Delay-Timing
      3. 9.1.3 RESET Latch Mode
      4. 9.1.4 Adjustable Voltage Thresholds
      5. 9.1.5 Immunity to SENSE Pin Voltage Transients
        1. 9.1.5.1 Hysteresis
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1: Multi-Rail Window Monitoring for Microcontroller Power Rails
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Design 2: RESET Latch Mode
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Guidelines
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Evaluation Module
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 用語集
  13. 13Mechanical, Packaging, and Orderable Information

Programmable Reset Delay-Timing

The TPS3703 reset time delay is based on internal current source (ICT) to charge external capacitor (CCT) and read capacitor voltage with internal comparator. The minium value capacitor is 250 pF. There is no limitation on maximum capacitor the only constrain is imposed by the initial voltage of the capacitor, if CT cap is zero or near to zero then ideally there is no other constraint on the max capacitor. The typical ideal capacitor value needed for a given delay time can be calculated using Equation 1, where CCT is in nanofarads (nF) and tD is in ms:

Equation 1. tD = 3.066 × CCT + 0.5 ms

To calculate the minimum and maximum-reset delay time use Equation 2 and Equation 3, respectively.

Equation 2. tD(min) = 2.7427 × CCT + 0.3 ms
Equation 3. tD(max) = 3.4636 × CCT + 0.7 ms

The slope of the equation is determined by the time the CT charging current (ICT) takes to charge the external capacitor up to the CT comparator threshold voltage (VCT). When RESET is asserted, the capacitor is discharged through the internal CT pulldown resistor. When the RESET conditions are cleared, the internal precision current source is enabled and begins to charge the external capacitor; when VCT = 1.15 V, RESET is unasserted. Note that in order to minimize the difference between the calculated RESET delay time and the actual RESET delay time, use a use a high-quality ceramic dielectric COG, X5R, or X7R capacitor and minimize parasitic board capacitance around this pin. Table 9-2 lists the reset delay time ideal capacitor values for CCT.

Table 9-2 Reset Delay Time for Ideal Capacitor Values
CCTRESET DELAY TIME (tD), TYPICAL
250 pF1.27 ms
1 nF3.57 ms
3.26 nF10.5 ms
32.6 nF100.45 ms
65.2 nF200.40 ms
1uF3066.50 ms