JAJSH28D November   2013  – March 2019 LM3697

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      昇圧効率
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 PWM Input
      2. 7.1.2 HWEN Input
      3. 7.1.3 Thermal Shutdown
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Descriptions
      1. 7.3.1 High-Voltage LED Control
        1. 7.3.1.1 High-Voltage Boost Converter
        2. 7.3.1.2 High-Voltage Current Sinks (HVLED1, HVLED2 and HVLED3)
        3. 7.3.1.3 High-Voltage Current String Biasing
      2. 7.3.2 Boost Switching-Frequency Select
      3. 7.3.3 Automatic Switching Frequency Shift
      4. 7.3.4 Brightness Register Current Control
        1. 7.3.4.1 8-Bit Control (Preferred)
        2. 7.3.4.2 11-Bit Control
      5. 7.3.5 PWM Control
        1. 7.3.5.1 PWM Input Frequency Range
        2. 7.3.5.2 PWM Input Polarity
        3. 7.3.5.3 PWM Zero Detection
      6. 7.3.6 Start-up/Shutdown Ramp
      7. 7.3.7 Run-Time Ramp
      8. 7.3.8 High-Voltage Control A and B Ramp Select
    4. 7.4 Device Functional Modes
      1. 7.4.1 LED Current Mapping Modes
        1. 7.4.1.1 Exponential Mapping
          1. 7.4.1.1.1 8-Bit Code Calculation
          2. 7.4.1.1.2 11-Bit Code Calculation
        2. 7.4.1.2 Linear Mapping
          1. 7.4.1.2.1 8-Bit Code Calculation
          2. 7.4.1.2.2 11-Bit Code Calculation
      2. 7.4.2 Fault Flags/Protection Features
        1. 7.4.2.1 Open LED String (HVLED)
        2. 7.4.2.2 Shorted LED String (HVLED)
        3. 7.4.2.3 Overvoltage Protection (Inductive Boost)
        4. 7.4.2.4 Current Limit (Inductive Boost)
      3. 7.4.3 I2C-Compatible Interface
        1. 7.4.3.1 Start And Stop Conditions
        2. 7.4.3.2 I2C-Compatible Address
        3. 7.4.3.3 Transferring Data
        4. 7.4.3.4 High-Speed Mode
    5. 7.5 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Boost Converter Maximum Output Power
          1. 8.2.2.1.1 Peak Current Limited
          2. 8.2.2.1.2 Output Voltage Limited
        2. 8.2.2.2 Inductor Selection
        3. 8.2.2.3 Output Capacitor Selection
        4. 8.2.2.4 Schottky Diode Selection
        5. 8.2.2.5 Input Capacitor Selection
        6. 8.2.2.6 Application Circuit Component List
      3. 8.2.3 Application Performance Plots
    3. 8.3 Initialization Set Up
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Boost Output Capacitor Placement
      2. 10.1.2 Schottky Diode Placement
      3. 10.1.3 Inductor Placement
      4. 10.1.4 Boost Input Capacitor Placement
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 11.2 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

6.5 Electrical Characteristics

Limits apply over the full operating ambient temperature range (−40°C ≤ TA ≤ 85°C) and VIN = 3.6 V, unless otherwise specified.(1)(2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ISHDN Shutdown current 2.7 V ≤ VIN ≤ 5.5 V, HWEN = GND 3 µA
TA = 25°C 1
ILED_MIN Minimum LED current Full-scale current = 20.2 mA
Exponential mapping, TA = 25°C		 6 µA
TSD Thermal shutdown 140 °C
Hysteresis 15
BOOST CONVERTER
IHVLED(1/2/3) Output current regulation (HVLED1, HVLED2, HVLED3) Full-scale current= 20.2 mA,
Exponential mapping,
Brightness Code = maximum 		2.7 V ≤ VIN ≤ 5.5 V 18.38 20.2 22.02 mA
Full-scale current= 20.2 mA,
Exponential mapping,
Brightness Code = maximum
HVLED1 Bank A, HVLED2/3 Bank B		 TA = 25°C –3.4% ±2 % 3.2%
TA = 25°C
3 V ≤ VIN ≤ 4.5 V		 –3.6% 3.4%
TA = 25°C ±2 %
IMATCH_HV HVLED1 to HVLED2 or HVLED3 matching (3) Exponential mapping,
auto headroom off,
PWM Off,
HVLED1/2/3 Bank A 		2.7 V ≤ VIN ≤ 5.5 V
ILED = 20.2 mA		 −2.5% 2.5%
TA = 25°C
ILED = 20.2 mA		 –2% 1.7%
2.7 V ≤ VIN ≤ 5.5 V
ILED = 500 µA		 –8.5% 8.5%
VREG_CS Regulated current sink headroom voltage Auto-headroom off, TA = 25°C 400 mV
VHR_MIN Minimum current sink headroom voltage for HVLED current sinks ILED = 95% of nominal, Full-scale current = 20.2 mA 275 mV
ILED = 95% of nominal, Full-scale current =
20.2 mA , TA = 25°C		 190
RDSON NMOS switch on resistance ISW = 500 mA, TA = 25°C 0.3 Ω
ICL_BOOST NMOS switch current limit 880 1120 mA
TA = 25°C 1000
VOVP Output overvoltage protection ON Threshold
OVP select bits = 11		 2.7 V ≤ VIN ≤ 5.5 V 38.75 41.1 V
TA = 25°C 40
Hysteresis TA = 25°C 1
ƒSW Switching frequency Boost frequency select bit = 0 2.7 V ≤ VIN ≤ 5.5 V 450 550 kHz
TA = 25°C 500
Boost frequency select bit = 1 2.7 V ≤ VIN ≤ 5.5 V 900 1100
TA = 25°C 1000
DMAX Maximum duty cycle TA = 25°C 94%
HWEN INPUT
VHWEN_L Logic low 2.7 V ≤ VIN ≤ 5.5 V 0 0.4 V
VHWEN_H Logic high 2.7 V ≤ VIN ≤ 5.5 V 1.2 VIN
PWM INPUT
VPWM_L Input logic low 2.7 V ≤ VIN ≤ 5.5 V 0 0.4 V
VPWM_H Input logic high 2.7V ≤ VIN ≤ 5.5 V 1.31 VIN
tPWM Minimum PWM input pulse 2.7 V ≤ VIN ≤ 5.5 V, PWM zero detect enabled 0.75 µs
I2C-COMPATIBLE VOLTAGE SPECIFICATIONS (SCL, SDA)
VIL Input logic low 2.7 V ≤ VIN ≤ 5.5 V 0 0.4 V
VIH Input logic high 2.7 V ≤ VIN ≤ 5.5 V 1.29 VIN
VOL Output logic low (SDA) 2.7 V ≤ VIN ≤ 5.5 V, ILOAD = 3 mA 400 mV
(1) All voltages are with respect to the potential at the GND pin.
(2) Minimum and Maximum limits are verified by design, test, or statistical analysis. Typical numbers are not verified, but do represent the most likely norm. Unless otherwise specified, conditions for typical specifications are: VIN = 3.6 V and TA = 25°C.
(3) LED current sink matching in the high-voltage current sinks (HVLED1 through HVLED3) is given as the maximum matching value between any two current sinks, where the matching between any two high voltage current sinks (X and Y) is given as (IHVLEDX ( or IHVLEDY) × IAVE(X-Y))/(IAVE(X-Y)) × 100. In this test all three HVLED current sinks are assigned to Bank A.