JAJSJD1D February   2022  – March 2023 TIOL112 , TIOL1123 , TIOL1125

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 ESD Ratings - IEC Specifications
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1  Wake-Up Detection
      2. 8.3.2  Current Limit Configuration
      3. 8.3.3  Current Fault Detection, Indication and Auto Recovery
      4. 8.3.4  Thermal Warning, Thermal Shutdown
      5. 8.3.5  Fault Reporting (NFAULT)
      6. 8.3.6  Transceiver Function Tables
      7. 8.3.7  The Integrated Voltage Regulator (LDO)
      8. 8.3.8  Reverse Polarity Protection
      9. 8.3.9  Integrated Surge Protection and Transient Waveform Tolerance
      10. 8.3.10 Power Up Sequence (TIOL112)
      11. 8.3.11 Undervoltage Lock-Out (UVLO)
    4. 8.4 Device Functional Modes
      1. 8.4.1 NPN Configuration (N-Switch SIO Mode)
      2. 8.4.2 PNP Configuration (P-Switch SIO Mode)
      3. 8.4.3 Push-Pull, Communication Mode
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Maximum Junction Temperature Check
        2. 9.2.2.2 Driving Capacitive Loads
        3. 9.2.2.3 Driving Inductive Loads
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  11. 11Mechanical, Packaging, and Orderable Information

Layout Guidelines

  • Use of a 4-layer board is recommended for good heat conduction. Use layer 1 (top layer) for control signals, layer 2 as power ground layer for L-, layer 3 for the 24-V supply plane (L+), and layer 4 for the regulated output supply (VCC_IN/OUT).
  • Connect the thermal pad to L- with maximum amount of thermal vias for best thermal performance.
  • Use entire planes for L+, VCC_IN/OUT and L- to assure minimum inductance.
  • The L+ terminal must be decoupled to ground with a low-ESR ceramic decoupling capacitor. The recommended minimum capacitor value is 100 nF. The capacitor must have a voltage rating of 50 V minimum (100 V depending on max sensor supply fault rating) and an X5R or X7R dielectric.
  • The optimum placement of the capacitor is closest to the transceiver’s L+ and L- terminals to reduce supply drops during large supply current loads. See Figure 9-9 for a PCB layout example.
  • Connect all open-drain control outputs via 10 kΩ pull-up resistors to the VCC_IN/OUT plane to provide a defined voltage potential to the system controller inputs when the outputs are high-impedance.
  • Connect the RSET resistor between ILIM_ADJ and L-.
  • Decouple the regulated output voltage at VCC_IN/OUT to ground with a low-ESR, ≥ 1-μF, ceramic decoupling capacitor. The capacitor should have a voltage rating of 10 V minimum and an X5R or X7R dielectric.