JAJSK58D January   2022  – April 2024 TPS4811-Q1

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Charge Pump and Gate Driver output (VS, PU, PD, BST, SRC)
      2. 8.3.2  Capacitive Load Driving
        1. 8.3.2.1 FET Gate Slew Rate Control
        2. 8.3.2.2 Using Precharge FET - (with TPS48111-Q1 Only)
      3. 8.3.3  Short-Circuit Protection
        1. 8.3.3.1 Overcurrent Protection With Auto-Retry
        2. 8.3.3.2 Overcurrent Protection With Latch-Off
      4. 8.3.4  Short-Circuit Protection
      5. 8.3.5  Analog Current Monitor Output (IMON)
      6. 8.3.6  Overvoltage (OV) and Undervoltage Protection (UVLO)
      7. 8.3.7  Device Functional Mode (Shutdown Mode)
      8. 8.3.8  Remote Temperature sensing and Protection (DIODE)
      9. 8.3.9  Output Reverse Polarity Protection
      10. 8.3.10 TPS4811x-Q1 as a Simple Gate Driver
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application: Driving HVAC PTC Heater Load on KL40 Line in Power Distribution Unit
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Typical Application: Driving B2B FETs With Pre-charging the Output Capacitance
      1. 9.3.1 Design Requirements
      2. 9.3.2 External Component Selection
      3. 9.3.3 Application Curves
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 ドキュメントの更新通知を受け取る方法
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Short-Circuit Protection

The TPS12000-Q1 feature adjustable short circuit protection. The threshold and the response time can be adjusted using ISCP resistor and TMR capacitor respectively. The device senses the voltage across the CS+ and CS– pins. These pins can be connected across an external current sense resistor or across the FET drain and source terminals for FET RDSON sensing. Set the circuit breaker detection threshold using an external resistor RISCP across ISCP and GND. Use Equation 6 to calculate the required RISCP value.

Equation 6. TPS4811-Q1

Where, RSNS is the current sense resistor value or the FET RDSON value, ISC is the short circuit current level. The short circuit protection response is fastest < 6 µs with no CTMR cap connected across TMR and GND pins.

In the configurations of high side current sense with CS_SEL connected to GND, during Q1 turn ON, first the FET’s VGS is sensed by monitoring the voltage across PD to SRC. Once VGS raises above G1_GOOD threshold to ensure that the external FET gate is enhanced, then the SCP comparator output is monitored. If the sensed voltage across CS+ and CS– exceeds the ISCP set point, PD pulls low to SRC and FLT asserts low within 6μs (with TMR open). Subsequent events can be set either to be auto-retry or latch off as described in following sections

With CS_SEL connected to >2V i.e low side current sense configurations, the device does not wait for the FETs to enhance (doesnot wait for G1_GOOD threshold to reach) and directly looks at the SCP comparator output to pull PD to SRC in the case of a short circuit event.