JAJSM45 June   2021 TMUX646

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 1.2-V Logic Compatible Inputs
      2. 8.3.2 Bidirectional Operation
      3. 8.3.3 Powered-Off Protection
      4. 8.3.4 Low Power Disable Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pin Functions
      2. 8.4.2 Low Power Disable Mode
      3. 8.4.3 Switch Enabled Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 MIPI D-PHY Application
        2. 9.2.2.2 MIPI C-PHY Application
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

Figure 5-1 nFBGA Package36 Pin (ZEC)Top View
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
CLKAN F3 I/O Differential I/O
CLKAP F4 I/O Differential I/O
CLKBN F1 I/O Differential I/O
CLKBP F2 I/O Differential I/O
CLKN F5 I/O Differential I/O
CLKP F6 I/O Differential I/O
D1N E5 I/O Differential I/O
D1P E6 I/O Differential I/O
D2N D5 I/O Differential I/O
D2P D6 I/O Differential I/O
D3N C5 I/O Differential I/O
D3P C6 I/O Differential I/O
D4N B5 I/O Differential I/O
D4P B6 I/O Differential I/O
DA1N E3 I/O Differential I/O
DA1P E4 I/O Differential I/O
DA2N D3 I/O Differential I/O
DA2P D4 I/O Differential I/O
DA3N B3 I/O Differential I/O
DA3P B4 I/O Differential I/O
DA4N A3 I/O Differential I/O
DA4P A4 I/O Differential I/O
DB1N E1 I/O Differential I/O
DB1P E2 I/O Differential I/O
DB2N D1 I/O Differential I/O
DB2P D2 I/O Differential I/O
DB3N C1 I/O Differential I/O
DB3P C2 I/O Differential I/O
DB4N B1 I/O Differential I/O
DB4P B2 I/O Differential I/O
GND A2 P Device Ground
NC C3 — No internal connection
NC C4 — No internal connection
OE A5 I Output enable (active low), has internal pull-down resistor
SEL A6 I Channel select, has internal pull-down resistor
VDD A1 P Power supply input