JAJSVA4B November   2004  – August 2024 CD74HC4538-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 概要
  4. 3 Pin Configuration and Functions
  5. 4 Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 Electrical Characteristics
    6. 4.6 Timing Requirements
    7. 4.7 Switching Characteristics
    8. 4.8 Operating Characteristics
    9. 4.9 Typical Characteristics
  6. 5 Parameter Measurement Information
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Typical Application
    2. 7.2 Power Supply Recommendations
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support (Analog)
      1. 8.1.1 Related Links
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

3 Pin Configuration and Functions

CD74HC4538-Q1 D or PW Package; 16-Pin SOIC or TSSOP (Top View) Figure 3-1 D or PW Package; 16-Pin SOIC or TSSOP (Top View)
Table 3-1 Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
1CX 1 — Connects to external capacitor
1RXCX 2 — Connects to external capacitor and resistor
1 1R 3 — Connects to external resistor
1A 4 I Ch1 Rising edge input
1B 5 I Ch1 Falling edge input
1Q 6 O Ch1 Output
1Q 7 O Ch1 Inverted Output
GND 8 — Ground
2Q 9 O Ch2 Inverted Output
2Q 10 O Ch2 Output
2B 11 I Ch2 Falling edge input
2A 12 I Ch2 Rising edge input
2R 13 — Connects to external resistor
2RXCX 14 — Connects to external capacitor and resistor
2CX 15 — Connects to external capacitor
VCC 16 — Power Pin