JAJSVM7A June   2023  – November 2024 UCC28731-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
    1.     Pin Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Detailed Pin Description
        1. 6.3.1.1 VDD (Device Bias Voltage Supply)
        2. 6.3.1.2 GND (Ground)
        3. 6.3.1.3 HV (High Voltage Startup)
        4. 6.3.1.4 DRV (Gate Drive)
        5. 6.3.1.5 CBC (Cable Compensation)
        6. 6.3.1.6 VS (Voltage Sense)
        7. 6.3.1.7 CS (Current Sense)
      2. 6.3.2 Primary-Side Regulation (PSR)
      3. 6.3.3 Primary-Side Constant Voltage Regulation
      4. 6.3.4 Primary-Side Constant Current Regulation
      5. 6.3.5 Valley-Switching and Valley-Skipping
      6. 6.3.6 Startup Operation
      7. 6.3.7 Fault Protection
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Input Bulk Capacitance and Minimum Bulk Voltage
        2. 7.2.2.2 Transformer Turns Ratio, Inductance, Primary-Peak Current
        3. 7.2.2.3 Transformer Parameter Verification
        4. 7.2.2.4 Output Capacitance
        5. 7.2.2.5 VDD Capacitance, CVDD
        6. 7.2.2.6 VS Resistor Divider, Line Compensation, and Cable Compensation
      3. 7.2.3 Application Curves
    3. 7.3 Do's and Don'ts
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
        1. 8.1.1.1  Capacitance Terms in Farads
        2. 8.1.1.2  Duty-Cycle Terms
        3. 8.1.1.3  Frequency Terms in Hertz
        4. 8.1.1.4  Current Terms in Amperes
        5. 8.1.1.5  Current and Voltage Scaling Terms
        6. 8.1.1.6  Transformer Terms
        7. 8.1.1.7  Power Terms in Watts
        8. 8.1.1.8  Resistance Terms in Ω
        9. 8.1.1.9  Timing Terms in Seconds
        10. 8.1.1.10 DC Voltage Terms in Volts
        11. 8.1.1.11 AC Voltage Terms in Volts
        12. 8.1.1.12 Efficiency Terms
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 サポート・リソース
    5. 8.5 Trademarks
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.3.1.6 VS (Voltage Sense)

The VS pin connects to a resistor-divider from the auxiliary winding to ground and is used to sense input voltage, output voltage, and event timing. The auxiliary voltage waveform is sampled at the end of the transformer secondary current demagnetization time to provide an accurate representation of the output voltage. The waveform on the VS pin determines the timing information to achieve valley-switching, and the timing to control the duty-cycle of the transformer secondary current when in Constant-Current Mode. Avoid placing a filter capacitor on this input which interferes with accurate sensing of this waveform.

During the MOSFET on-time, this pin also senses VS current generated through RS1 by the reflected bulk-capacitor voltage to provide for AC-input Run and Stop thresholds, and to compensate the current-sense threshold across the AC-input range. For the AC-input Run/Stop function, the Run threshold on VS is 225µA and the Stop threshold is 80µA.

At the end of off-time demagnetization, the reflected output voltage is sampled at this pin to provide regulation and overvoltage protection. The values for the auxiliary voltage-divider high-side-resistor, RS1, and lower-resistor, RS2, are determined by Equation 2 and Equation 3.

Equation 2. UCC28731-Q1

where

  • VIN(run) is the target AC RMS voltage to enable turn-on of the controller (Run) (in case of DC input, leave out the √2 term in the equation),
  • IVSL(run) is the Run-threshold for the current pulled out of the VS pin during the switch on-time (see Section 5.5),
  • NPA is the transformer primary-to-auxiliary turns-ratio.
Equation 3. UCC28731-Q1

where

  • VOCV is the converter regulated output voltage,
  • VF is the output rectifier forward drop at near-zero current,
  • NAS is the transformer auxiliary-to-secondary turns-ratio,
  • RS1 is the VS divider high-side resistance,
  • VVSR is the CV regulating level at the VS input (see Section 5.5).

When the UCC28730-Q1 is operating in the Wait state, the VS input is receptive to a wake-up signal superimposed upon the auxiliary winding waveform after the waveform meets either of two qualifying conditions. A high-level wake-up signal is considered to be detected if the amplitude at the VS input exceeds VWU(high) (2V) provided that any voltage at VS has been continuously below VWU(high) for the wake-up qualification delay tWDLY (8.5μs) after the demagnetization interval. A low-level wake-up signal is considered to be detected if the amplitude at the VS input exceeds VWU(low) (57mV) provided that any voltage at VS has been continuously below VWU(low) for the wake-up qualification delay tWDLY (8.5μs) after the demagnetization interval. The high\u0002level threshold accommodates signals generated by a low-impedance secondary-side driver while the low-level threshold detects signals generated by a high-impedance driver