JAJSW96B May   2005  – March 2025 TPIC6596

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Dissipation Rating Table
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Electrical Characteristics
    5. 5.5 Switching Characteristics
    6. 5.6 Thermal Resistance Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Serial-In Interface
      2. 7.3.2 Clear Register
      3. 7.3.3 Output Control
      4. 7.3.4 Cascaded Application
      5. 7.3.5 Current Limit Function
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operating with Vcc < 4.5V
      2. 7.4.2 Operating with 5.5V < Vcc ≤ 7V
  9. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

TPIC6596 DW or N Package, 20-pin SOIC (Top- View) Figure 4-1 DW or N Package, 20-pin SOIC (Top- View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
DRAIN0 4 O Open-drain output
DRAIN1 5
DRAIN2 6
DRAIN3 7
DRAIN4 14
DRAIN5 15
DRAIN6 16
DRAIN7 17
G 9 I Output enable, active-low
LGND 19 - Logic ground
PGND 1, 10, 11, 20 - Power ground
RCK 12 I Register clock
SER IN 3 I Serial data input
SER OUT 18 O Serial data output
SRCK 13 I Shift register clock
SRCLR 8 I Shift register clear, active-low
VCC 2 I Power supply
(1) P: Power Pin; I: Input Pin; I/O: Input/Output Pin; O: Output Pin.