SBOA384 September   2020 TLV9062-Q1 , TLV9064-Q1

 

  1.   Trademarks
  2. 1Overview
  3. 2Functional Safety Failure In Time (FIT) Rates
    1. 2.1 SOIC (8) Package
    2. 2.2 VSSOP (8) Package
    3. 2.3 SOIC (14) Package
    4. 2.4 TSSOP (14) Package
  4. 3Failure Mode Distribution (FMD)
  5. 4Pin Failure Mode Analysis (Pin FMA)
    1. 4.1 SOIC (8) and VSSOP (8) Packages
    2. 4.2 TSSOP (14) and SOIC (14) Packages

Failure Mode Distribution (FMD)

The failure mode distribution estimation for TLV9062-Q1 and TLV9064-Q1 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity and from best engineering judgment.

The failure modes listed in this section reflect random failure events and do not include failures due to misuse or overstress.

Table 3-1 Die Failure Modes and Distribution
Die Failure ModesFailure Mode Distribution (%)
Out open (HIZ)15%
Out saturate high25%
Out saturate low25%
Out functional not in specification voltage or timing30%
Short circuit any two pins5%