SBOA384 September   2020 TLV9062-Q1 , TLV9064-Q1

 

  1.   Trademarks
  2. 1Overview
  3. 2Functional Safety Failure In Time (FIT) Rates
    1. 2.1 SOIC (8) Package
    2. 2.2 VSSOP (8) Package
    3. 2.3 SOIC (14) Package
    4. 2.4 TSSOP (14) Package
  4. 3Failure Mode Distribution (FMD)
  5. 4Pin Failure Mode Analysis (Pin FMA)
    1. 4.1 SOIC (8) and VSSOP (8) Packages
    2. 4.2 TSSOP (14) and SOIC (14) Packages

Pin Failure Mode Analysis (Pin FMA)

This section provides a Failure Mode Analysis (FMA) for the pins of the TLV9062-Q1 (SOIC (8) and VSSOP (8) packages) and TLV9064-Q1 (TSSOP (14) and SOIC (14) packages). The failure modes covered in this document include the typical pin-by-pin failure scenarios:

Table 4-2 through Table 4-8 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects
ClassFailure Effects
APotential device damage that affects functionality
BNo device damage, but loss of functionality
CNo device damage, but performance degradation
DNo device damage, no impact to functionality or performance