SBOA384 September   2020 TLV9062-Q1 , TLV9064-Q1

 

  1.   Trademarks
  2. 1Overview
  3. 2Functional Safety Failure In Time (FIT) Rates
    1. 2.1 SOIC (8) Package
    2. 2.2 VSSOP (8) Package
    3. 2.3 SOIC (14) Package
    4. 2.4 TSSOP (14) Package
  4. 3Failure Mode Distribution (FMD)
  5. 4Pin Failure Mode Analysis (Pin FMA)
    1. 4.1 SOIC (8) and VSSOP (8) Packages
    2. 4.2 TSSOP (14) and SOIC (14) Packages

4.2 TSSOP (14) and SOIC (14) Packages

Figure 4-2 shows the TLV9064-Q1 pin diagram for the TSSOP (14) and SOIC (14) packages. For a detailed description of the device pins please refer to the 'Pin Configuration and Functions' section in the TLV9064-Q1 data sheet.

Figure 4-2 Pin Diagram (TSSOP (14) and SOIC (14) Packages)
Table 4-6 Pin FMA for Device Pins Short-Circuited to (V-)
Pin Name Pin No. Description of Potential Failure Effect(s) Failure Effect Class
OUT1 1 May cause overheating. B
IN1- 2 Input at V- is valid input, however, desired application result is unlikely. C
IN1+ 3 Input at V- is valid input, however, desired application result is unlikely. C
(V+) 4 Diodes from input to V+ may turn due to input signal and cause EOS. B
IN2+ 5 Input at V- is valid input, however, desired application result is unlikely. C
IN2- 6 Input at V- is valid input, however, desired application result is unlikely. C
OUT2 7 May cause overheating. B
OUT3 8 May cause overheating. B
IN3- 9 Input at V- is valid input, however, desired application result is unlikely. C
IN3+ 10 Input at V- is valid input, however, desired application result is unlikely. C
(V-) 11 Normal operation. D
IN4+ 12 Input at V- is valid input, however, desired application result is unlikely. C
IN4- 13 Input at V- is valid input, however, desired application result is unlikely. C
OUT4 14 May cause overheating. B
Table 4-7 Pin FMA for Device Pins Open-Circuited
Pin Name Pin No. Description of Potential Failure Effect(s) Failure Effect Class
OUT1 1 Output can't be used by application. C
IN1- 2 Floating input, circuit will likely not function as expected. C
IN1+ 3 Floating input, circuit will likely not function as expected. C
(V+) 4 Highest voltage pin will try to power internal ground via ESD diode to VCC. B
IN2+ 5 Floating input, circuit will likely not function as expected. C
IN2- 6 Floating input, circuit will likely not function as expected. C
OUT2 7 Output can't be used by application. C
OUT3 8 Output can't be used by application. C
IN3- 9 Floating input, circuit will likely not function as expected. C
IN3+ 10 Floating input, circuit will likely not function as expected. C
(V-) 11 Lowest voltage pin will try to power internal ground via ESD diode to ground. B
IN4+ 12 Floating input, circuit will likely not function as expected. C
IN4- 13 Floating input, circuit will likely not function as expected. C
OUT4 14 Output can't be used by application. C
Table 4-8 Pin FMA for Device Pins Short-Circuited to (V+)
Pin NamePin No.Description of Potential Failure Effect(s)Failure Effect Class
OUT11May cause overheating.B
IN1-2Input at V+ is valid input, however, desired application result is unlikely.C
IN1+3Input at V+ is valid input, however, desired application result is unlikely.C
(V+)4Normal operation.D
IN2+5Input at V+ is valid input, however, desired application result is unlikely.C
IN2-6Input at V+ is valid input, however, desired application result is unlikely.C
OUT27May cause overheating.B
OUT38May cause overheating.B
IN3-9Input at V+ is valid input, however, desired application result is unlikely.C
IN3+10Input at V+ is valid input, however, desired application result is unlikely.C
(V-) 11 Diodes from input to V- may turn due to input signal and cause EOS. B
IN4+ 12 Input at V+ is valid input, however, desired application result is unlikely. C
IN4- 13 Input at V+ is valid input, however, desired application result is unlikely. C
OUT4 14 May cause overheating. B
Table 4-9 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
Pin Name Pin No. Shorted to Description of Potential Failure Effect(s) Failure Effect Class
OUT1 1 IN1- Negative feedback, creates unity gain buffer. C
IN1- 2 IN1+ No damage to device, application circuit won't work. C
IN1+ 3 (V+) Input at V+ is valid input, however, desired application result is unlikely. C
(V+) 4 IN2+ Input at V+ is valid input, however, desired application result is unlikely. C
IN2+ 5 IN2- No damage to device, application circuit won't work. C
IN2- 6 OUT2 Negative feedback, creates unity gain buffer. C
OUT2 7 OUT3 May cause overheating (pins on opposite sides, not adjacent). B
OUT3 8 IN3- Negative feedback, creates unity gain buffer. C
IN3- 9 IN3+ No damage to device, application circuit won't work. C
IN3+ 10 (V-) Input at ground is valid input, however, desired application result is unlikely. C
(V-) 11 IN4+ CH 4 output high, if other input is valid common mode range. C
IN4+ 12 IN4- No damage to device, application circuit won't work. C
IN4- 13 OUT4 Negative feedback, creates unity gain buffer. C
OUT4 14 OUT1 May cause overheating (pins on opposite sides, not adjacent). B