SBOU162A March   2017  – May 2017

 

  1.   DIYAMP-SOIC-EVM
    1.     Trademarks
    2. 1 Introduction
      1. 1.1 DIYAMP-SOIC-EVM Kit Contents
      2. 1.2 EVM Features
      3. 1.3 List of Circuits on the EVM
    3. 2 Hardware Setup
      1. 2.1 EVM Circuit Locations
      2. 2.2 EVM Assembly Instructions
    4. 3 Schematic and PCB Layout
      1. 3.1  Schematic PCB Drawing
      2. 3.2  Single-Supply, Multiple Feedback Filter
      3. 3.3  Single-Supply, Sallen-Key Filter
      4. 3.4  Single-Supply, Non-Inverting Amplifier
      5. 3.5  Single-Supply, Inverting Amplifier
      6. 3.6  Difference Amplifier
      7. 3.7  Dual-Supply, Multiple Feedback Filter
      8. 3.8  Dual-Supply, Sallen-Key Filter
      9. 3.9  Inverting Comparator
      10. 3.10 Non-Inverting Comparator
      11. 3.11 Riso With Dual Feedback
      12. 3.12 Dual-Supply, Non-Inverting Amplifier
      13. 3.13 Dual-Supply, Inverting Amplifier
    5. 4 Connections
      1. 4.1 Inputs and Outputs
      2. 4.2 Power
      3. 4.3 Enable and Disable Feature
    6. 5 Bill of Materials and Reference
      1. 5.1 Bill of Materials
      2. 5.2 Reference
  2.   Revision History

3.5 Single-Supply, Inverting Amplifier

Figure 18 shows the schematic for the single-supply, inverting amplifier circuit configuration.

fig11_sbou162.pngFigure 18. Single-Supply, Inverting Amplifier Schematic

The inverting op-amp configuration takes an input signal that is applied directly to the inverting input terminal and outputs a signal that is the opposite polarity as the input signal. The benefit of this topology is that it avoids common mode limitations. The load resistance for this topology is equal to R2. The values of the resistors in the feedback network will determine the amount of gain to amplify the input signal.

The single-supply, inverting amplifier circuit provides the option to AC couple the input, filter the output, and bias the output of the amplifier to a desired value.

Equation 9 displays the dc transfer function of the single-supply, inverting amplifier circuit configuration.

Equation 9. nneq09_sbou162.gif

    where

  • C3 is shorted with a 0-Ω resistor

Capacitor C3 provides the option to AC couple the input of the single-supply, inverting amplifier by creating a high-pass filter. Equation 10 displays the dc transfer function of the single-supply, inverting amplifier circuit configuration.

Equation 10. neq23_sbou162.gif

    where

  • The input is AC coupled with C3

The cutoff frequency of the high-pass filter can be calculated using Equation 11.

Equation 11. neq24_sbou162.gif

Equation 12 displays the transfer function when the frequency of the input signal is above the cutoff frequency calculated in Equation 11.

Equation 12. neq25_sbou162.gif

Capacitor C2 filters noise that may be introduced from the Vref input. Equation 13 calculates the cutoff frequency due to C2.

Equation 13. eq22_sbou162.gif

Capacitor C4 provides the option to filter the output. The cutoff frequency of the filter can be calculated using Equation 14.

Equation 14. nneq14_sbou162.gif

The PCB layout of the top layer of the single-supply, inverting amplifier circuit configuration is displayed in Figure 19.

fig19_sbou162.gifFigure 19. Single-Supply, Inverting Amplifier Top Layer

The PCB layout of the bottom layer of the single-supply, inverting amplifier circuit configuration is displayed in Figure 20.

diyamp_nfig20_SS_inv_amp_bottomlayer.pngFigure 20. Single-Supply, Inverting Amplifier Bottom Layer